a33e311a3b
When deciding the safety of generating smlad, we checked for any writes within the block that may alias with any of the loads that need to be widened. This is overly conservative because it only matters when there's a potential aliasing write to a location accessed by a pair of loads. Now we check for aliasing writes only once, during setup. If two loads are found to have an aliasing write between them, we don't add these loads to LoadPairs. This means that later during the transform, we can safely widened a pair without worrying about aliasing. However, to maintain correctness, we also need to change the way that wide loads are inserted because the order is now important. The MatchSMLAD method has also been changed, absorbing MatchReductions and AddMACCandidate to hopefully improve readability. Differential Revision: https://reviews.llvm.org/D6102 llvm-svn: 360567
77 lines
3.2 KiB
LLVM
77 lines
3.2 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S -stats 2>&1 | FileCheck %s
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;
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; A more complicated chain: 4 mul operations, so we expect 2 smlad calls.
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;
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; CHECK: %mac1{{\.}}054 = phi i32 [ [[V17:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
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; CHECK: [[V10:%[0-9]+]] = bitcast i16* %arrayidx to i32*
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; CHECK: [[V11:%[0-9]+]] = load i32, i32* [[V10]], align 2
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; CHECK: [[V15:%[0-9]+]] = bitcast i16* %arrayidx4 to i32*
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; CHECK: [[V16:%[0-9]+]] = load i32, i32* [[V15]], align 2
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; CHECK: [[V8:%[0-9]+]] = bitcast i16* %arrayidx8 to i32*
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; CHECK: [[V9:%[0-9]+]] = load i32, i32* [[V8]], align 2
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; CHECK: [[V13:%[0-9]+]] = bitcast i16* %arrayidx17 to i32*
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; CHECK: [[V14:%[0-9]+]] = load i32, i32* [[V13]], align 2
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; CHECK: [[V12:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V9]], i32 [[V11]], i32 %mac1{{\.}}054)
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; CHECK: [[V17:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V14]], i32 [[V16]], i32 [[V12]])
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;
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; And we don't want to see a 3rd smlad:
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; CHECK-NOT: call i32 @llvm.arm.smlad
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;
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; CHECK: 2 arm-parallel-dsp - Number of smlad instructions generated
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;
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define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
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entry:
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%cmp52 = icmp sgt i32 %arg, 0
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br i1 %cmp52, label %for.body.preheader, label %for.cond.cleanup
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for.cond.cleanup:
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%mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add28, %for.body ]
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ret i32 %mac1.0.lcssa
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for.body.preheader:
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br label %for.body
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for.body:
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%mac1.054 = phi i32 [ %add28, %for.body ], [ 0, %for.body.preheader ]
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%i.053 = phi i32 [ %add29, %for.body ], [ 0, %for.body.preheader ]
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%arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.053
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%0 = load i16, i16* %arrayidx, align 2
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%add1 = or i32 %i.053, 1
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%arrayidx2 = getelementptr inbounds i16, i16* %arg3, i32 %add1
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%1 = load i16, i16* %arrayidx2, align 2
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%add3 = or i32 %i.053, 2
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%arrayidx4 = getelementptr inbounds i16, i16* %arg3, i32 %add3
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%2 = load i16, i16* %arrayidx4, align 2
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%add5 = or i32 %i.053, 3
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%arrayidx6 = getelementptr inbounds i16, i16* %arg3, i32 %add5
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%3 = load i16, i16* %arrayidx6, align 2
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%arrayidx8 = getelementptr inbounds i16, i16* %arg2, i32 %i.053
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%4 = load i16, i16* %arrayidx8, align 2
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%conv = sext i16 %4 to i32
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%conv9 = sext i16 %0 to i32
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%mul = mul nsw i32 %conv, %conv9
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%arrayidx11 = getelementptr inbounds i16, i16* %arg2, i32 %add1
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%5 = load i16, i16* %arrayidx11, align 2
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%conv12 = sext i16 %5 to i32
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%conv13 = sext i16 %1 to i32
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%mul14 = mul nsw i32 %conv12, %conv13
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%arrayidx17 = getelementptr inbounds i16, i16* %arg2, i32 %add3
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%6 = load i16, i16* %arrayidx17, align 2
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%conv18 = sext i16 %6 to i32
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%conv19 = sext i16 %2 to i32
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%mul20 = mul nsw i32 %conv18, %conv19
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%arrayidx23 = getelementptr inbounds i16, i16* %arg2, i32 %add5
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%7 = load i16, i16* %arrayidx23, align 2
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%conv24 = sext i16 %7 to i32
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%conv25 = sext i16 %3 to i32
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%mul26 = mul nsw i32 %conv24, %conv25
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%add15 = add i32 %mul, %mac1.054
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%add21 = add i32 %add15, %mul14
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%add27 = add i32 %add21, %mul20
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%add28 = add i32 %add27, %mul26
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%add29 = add nuw nsw i32 %i.053, 4
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%cmp = icmp slt i32 %add29, %arg
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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}
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