9681b01c21
The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32 (necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP, this will result in a FP load from the constant pool followed by a store to the stack and two integer loads from the stack (necessary as there is no way to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper to just materialise integers for the lo and hi parts of the FP constant, so do that instead. llvm-svn: 357341
145 lines
4.8 KiB
LLVM
145 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; Sanity checks for calling convention lowering for RV32D. This can be
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; somewhat error-prone for soft-float RV32D due to the fact that f64 is legal
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; but i64 is not, and there is no instruction to move values directly between
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; the GPRs and 64-bit FPRs.
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define double @callee_double_inreg(double %a, double %b) nounwind {
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; RV32IFD-LABEL: callee_double_inreg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 8(sp)
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; RV32IFD-NEXT: sw a3, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fadd double %a, %b
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ret double %1
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}
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; TODO: code quality for loading and then passing f64 constants is poor.
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define double @caller_double_inreg() nounwind {
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; RV32IFD-LABEL: caller_double_inreg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: lui a0, 262236
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; RV32IFD-NEXT: addi a1, a0, 655
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; RV32IFD-NEXT: lui a0, 377487
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; RV32IFD-NEXT: addi a0, a0, 1475
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; RV32IFD-NEXT: lui a2, 262364
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; RV32IFD-NEXT: addi a3, a2, 655
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; RV32IFD-NEXT: mv a2, a0
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; RV32IFD-NEXT: call callee_double_inreg
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = call double @callee_double_inreg(double 2.720000e+00, double 3.720000e+00)
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ret double %1
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}
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define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d, double %e) nounwind {
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; RV32IFD-LABEL: callee_double_split_reg_stack:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: lw a0, 16(sp)
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; RV32IFD-NEXT: sw a7, 8(sp)
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; RV32IFD-NEXT: sw a0, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: sw a5, 8(sp)
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; RV32IFD-NEXT: sw a6, 12(sp)
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; RV32IFD-NEXT: fld ft1, 8(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fadd double %d, %e
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ret double %1
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}
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define double @caller_double_split_reg_stack() nounwind {
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; RV32IFD-LABEL: caller_double_split_reg_stack:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: lui a0, 262510
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; RV32IFD-NEXT: addi a0, a0, 327
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: lui a0, 262446
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; RV32IFD-NEXT: addi a6, a0, 327
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; RV32IFD-NEXT: lui a0, 713032
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; RV32IFD-NEXT: addi a5, a0, -1311
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; RV32IFD-NEXT: addi a0, zero, 1
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; RV32IFD-NEXT: addi a1, zero, 2
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; RV32IFD-NEXT: mv a2, zero
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; RV32IFD-NEXT: addi a3, zero, 3
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; RV32IFD-NEXT: mv a4, zero
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; RV32IFD-NEXT: mv a7, a5
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; RV32IFD-NEXT: call callee_double_split_reg_stack
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
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ret double %1
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}
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define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, double %f) nounwind {
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; RV32IFD-LABEL: callee_double_stack:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: fld ft0, 24(sp)
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; RV32IFD-NEXT: fld ft1, 16(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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%1 = fadd double %e, %f
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ret double %1
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}
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define double @caller_double_stack() nounwind {
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; RV32IFD-LABEL: caller_double_stack:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -32
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; RV32IFD-NEXT: sw ra, 28(sp)
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; RV32IFD-NEXT: lui a0, 262510
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; RV32IFD-NEXT: addi a0, a0, 327
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; RV32IFD-NEXT: sw a0, 4(sp)
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; RV32IFD-NEXT: lui a0, 262574
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; RV32IFD-NEXT: addi a0, a0, 327
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; RV32IFD-NEXT: sw a0, 12(sp)
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; RV32IFD-NEXT: lui a0, 713032
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; RV32IFD-NEXT: addi a0, a0, -1311
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: addi a0, zero, 1
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; RV32IFD-NEXT: mv a1, zero
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; RV32IFD-NEXT: addi a2, zero, 2
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; RV32IFD-NEXT: mv a3, zero
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; RV32IFD-NEXT: addi a4, zero, 3
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; RV32IFD-NEXT: mv a5, zero
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; RV32IFD-NEXT: addi a6, zero, 4
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; RV32IFD-NEXT: mv a7, zero
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; RV32IFD-NEXT: call callee_double_stack
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; RV32IFD-NEXT: lw ra, 28(sp)
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; RV32IFD-NEXT: addi sp, sp, 32
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; RV32IFD-NEXT: ret
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%1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
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ret double %1
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}
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