b9e78c3994
This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence often occurs when a SELECT of values wider than XLEN is legalized into two SELECTs with legal types. We have identified several use cases where the SELECTs could be interleaved with other instructions. Therefore, we extend the sequence to include non-SELECT instructions if we are able to detect that the non-SELECT instructions do not impact the optimization. This patch supersedes https://reviews.llvm.org/D59096, which attempted to address this issue by introducing a new SelectionDAG node. Hat tip to Eli Friedman for his feedback on how to best handle this issue. Differential Revision: https://reviews.llvm.org/D59355 Patch by Luís Marques. llvm-svn: 356741
324 lines
9.3 KiB
LLVM
324 lines
9.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Selects of wide values are split into two selects, which can easily cause
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; unnecessary control flow. Here we check some cases where we can currently
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; emit a sequence of selects with shared control flow.
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define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
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; RV32I-LABEL: cmovcc64:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: addi a5, zero, 123
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; RV32I-NEXT: beq a0, a5, .LBB0_2
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: mv a2, a4
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; RV32I-NEXT: .LBB0_2: # %entry
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: mv a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmovcc64:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi a3, zero, 123
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; RV64I-NEXT: beq a0, a3, .LBB0_2
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: mv a1, a2
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; RV64I-NEXT: .LBB0_2: # %entry
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: ret
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entry:
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%cmp = icmp eq i32 %a, 123
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%cond = select i1 %cmp, i64 %b, i64 %c
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ret i64 %cond
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}
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define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
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; RV32I-LABEL: cmovcc128:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: xori a1, a1, 123
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: beqz a1, .LBB1_2
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: addi a1, a4, 4
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; RV32I-NEXT: addi a2, a4, 8
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; RV32I-NEXT: addi a5, a4, 12
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; RV32I-NEXT: mv a3, a4
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; RV32I-NEXT: j .LBB1_3
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: addi a1, a3, 4
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; RV32I-NEXT: addi a2, a3, 8
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; RV32I-NEXT: addi a5, a3, 12
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; RV32I-NEXT: .LBB1_3: # %entry
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; RV32I-NEXT: lw a4, 0(a5)
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; RV32I-NEXT: sw a4, 12(a0)
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; RV32I-NEXT: lw a2, 0(a2)
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; RV32I-NEXT: sw a2, 8(a0)
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; RV32I-NEXT: lw a1, 0(a1)
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; RV32I-NEXT: sw a1, 4(a0)
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; RV32I-NEXT: lw a1, 0(a3)
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmovcc128:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi a5, zero, 123
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; RV64I-NEXT: beq a0, a5, .LBB1_2
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: mv a1, a3
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; RV64I-NEXT: mv a2, a4
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; RV64I-NEXT: .LBB1_2: # %entry
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: mv a1, a2
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; RV64I-NEXT: ret
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entry:
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%cmp = icmp eq i64 %a, 123
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%cond = select i1 %cmp, i128 %b, i128 %c
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ret i128 %cond
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}
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define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
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; RV32I-LABEL: cmov64:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: bnez a0, .LBB2_2
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: mv a2, a4
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; RV32I-NEXT: .LBB2_2: # %entry
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: mv a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmov64:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: bnez a0, .LBB2_2
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: mv a1, a2
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; RV64I-NEXT: .LBB2_2: # %entry
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: ret
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entry:
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%cond = select i1 %a, i64 %b, i64 %c
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ret i64 %cond
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}
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define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
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; RV32I-LABEL: cmov128:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: andi a1, a1, 1
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; RV32I-NEXT: bnez a1, .LBB3_2
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: addi a1, a3, 4
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; RV32I-NEXT: addi a4, a3, 8
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; RV32I-NEXT: addi a5, a3, 12
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; RV32I-NEXT: mv a2, a3
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; RV32I-NEXT: j .LBB3_3
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: addi a1, a2, 4
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; RV32I-NEXT: addi a4, a2, 8
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; RV32I-NEXT: addi a5, a2, 12
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; RV32I-NEXT: .LBB3_3: # %entry
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; RV32I-NEXT: lw a3, 0(a5)
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; RV32I-NEXT: sw a3, 12(a0)
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; RV32I-NEXT: lw a3, 0(a4)
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; RV32I-NEXT: sw a3, 8(a0)
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; RV32I-NEXT: lw a1, 0(a1)
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; RV32I-NEXT: sw a1, 4(a0)
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; RV32I-NEXT: lw a1, 0(a2)
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmov128:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: bnez a0, .LBB3_2
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: mv a1, a3
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; RV64I-NEXT: mv a2, a4
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; RV64I-NEXT: .LBB3_2: # %entry
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: mv a1, a2
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; RV64I-NEXT: ret
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entry:
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%cond = select i1 %a, i128 %b, i128 %c
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ret i128 %cond
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}
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define float @cmovfloat(i1 %a, float %b, float %c, float %d, float %e) nounwind {
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; RV32I-LABEL: cmovfloat:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: bnez a0, .LBB4_2
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: fmv.w.x ft0, a4
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; RV32I-NEXT: fmv.w.x ft1, a2
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; RV32I-NEXT: j .LBB4_3
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: fmv.w.x ft0, a3
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; RV32I-NEXT: fmv.w.x ft1, a1
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; RV32I-NEXT: .LBB4_3: # %entry
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; RV32I-NEXT: fadd.s ft0, ft1, ft0
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; RV32I-NEXT: fmv.x.w a0, ft0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmovfloat:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: bnez a0, .LBB4_2
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: fmv.w.x ft0, a4
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; RV64I-NEXT: fmv.w.x ft1, a2
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; RV64I-NEXT: j .LBB4_3
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: fmv.w.x ft0, a3
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; RV64I-NEXT: fmv.w.x ft1, a1
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; RV64I-NEXT: .LBB4_3: # %entry
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; RV64I-NEXT: fadd.s ft0, ft1, ft0
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; RV64I-NEXT: fmv.x.w a0, ft0
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; RV64I-NEXT: ret
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entry:
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%cond1 = select i1 %a, float %b, float %c
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%cond2 = select i1 %a, float %d, float %e
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%ret = fadd float %cond1, %cond2
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ret float %ret
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}
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define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
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; RV32I-LABEL: cmovdouble:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw a3, 8(sp)
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; RV32I-NEXT: sw a4, 12(sp)
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; RV32I-NEXT: fld ft0, 8(sp)
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; RV32I-NEXT: sw a1, 8(sp)
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; RV32I-NEXT: sw a2, 12(sp)
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; RV32I-NEXT: fld ft1, 8(sp)
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: bnez a0, .LBB5_2
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: fmv.d ft1, ft0
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; RV32I-NEXT: .LBB5_2: # %entry
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; RV32I-NEXT: fsd ft1, 8(sp)
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; RV32I-NEXT: lw a0, 8(sp)
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; RV32I-NEXT: lw a1, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmovdouble:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: bnez a0, .LBB5_2
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: fmv.d.x ft0, a2
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; RV64I-NEXT: fmv.x.d a0, ft0
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB5_2:
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; RV64I-NEXT: fmv.d.x ft0, a1
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; RV64I-NEXT: fmv.x.d a0, ft0
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; RV64I-NEXT: ret
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entry:
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%cond = select i1 %a, double %b, double %c
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ret double %cond
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}
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; Check that selects with dependencies on previous ones aren't incorrectly
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; optimized.
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define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32 %d) nounwind {
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; RV32I-LABEL: cmovccdep:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: addi a4, zero, 123
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; RV32I-NEXT: bne a0, a4, .LBB6_3
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: mv a2, a1
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; RV32I-NEXT: bne a0, a4, .LBB6_4
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; RV32I-NEXT: .LBB6_2: # %entry
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; RV32I-NEXT: add a0, a1, a2
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB6_3: # %entry
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; RV32I-NEXT: mv a1, a2
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; RV32I-NEXT: mv a2, a1
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; RV32I-NEXT: beq a0, a4, .LBB6_2
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; RV32I-NEXT: .LBB6_4: # %entry
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; RV32I-NEXT: mv a2, a3
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; RV32I-NEXT: add a0, a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmovccdep:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi a4, zero, 123
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; RV64I-NEXT: bne a0, a4, .LBB6_3
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: mv a2, a1
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; RV64I-NEXT: bne a0, a4, .LBB6_4
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; RV64I-NEXT: .LBB6_2: # %entry
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; RV64I-NEXT: add a0, a1, a2
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB6_3: # %entry
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; RV64I-NEXT: mv a1, a2
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; RV64I-NEXT: mv a2, a1
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; RV64I-NEXT: beq a0, a4, .LBB6_2
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; RV64I-NEXT: .LBB6_4: # %entry
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; RV64I-NEXT: mv a2, a3
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; RV64I-NEXT: add a0, a1, a2
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; RV64I-NEXT: ret
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entry:
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%cmp = icmp eq i32 %a, 123
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%cond1 = select i1 %cmp, i32 %b, i32 %c
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%cond2 = select i1 %cmp, i32 %cond1, i32 %d
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%ret = add i32 %cond1, %cond2
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ret i32 %ret
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}
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; Check that selects with different conditions aren't incorrectly optimized.
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define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
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; RV32I-LABEL: cmovdiffcc:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: andi a1, a1, 1
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; RV32I-NEXT: beqz a1, .LBB7_3
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: beqz a0, .LBB7_4
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; RV32I-NEXT: .LBB7_2: # %entry
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; RV32I-NEXT: add a0, a2, a4
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB7_3: # %entry
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; RV32I-NEXT: mv a4, a5
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: bnez a0, .LBB7_2
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; RV32I-NEXT: .LBB7_4: # %entry
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; RV32I-NEXT: mv a2, a3
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; RV32I-NEXT: add a0, a2, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: cmovdiffcc:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: andi a1, a1, 1
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; RV64I-NEXT: beqz a1, .LBB7_3
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; RV64I-NEXT: # %bb.1: # %entry
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: beqz a0, .LBB7_4
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; RV64I-NEXT: .LBB7_2: # %entry
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; RV64I-NEXT: add a0, a2, a4
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB7_3: # %entry
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; RV64I-NEXT: mv a4, a5
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: bnez a0, .LBB7_2
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; RV64I-NEXT: .LBB7_4: # %entry
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; RV64I-NEXT: mv a2, a3
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; RV64I-NEXT: add a0, a2, a4
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; RV64I-NEXT: ret
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entry:
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%cond1 = select i1 %a, i32 %c, i32 %d
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%cond2 = select i1 %b, i32 %e, i32 %f
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%ret = add i32 %cond1, %cond2
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ret i32 %ret
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}
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