8e42f6ddc8
This adds the FPC (floating-point control register) as a reserved physical register and models its use by SystemZ instructions. Note that only the current rounding modes and the IEEE exception masks are modeled. *Changes* of the FPC due to exceptions (in particular the IEEE exception flags and the DXC) are not modeled. At this point, this patch is mostly NFC, but it will prevent scheduling of floating-point instructions across SPFC/LFPC etc. llvm-svn: 360570
203 lines
8.3 KiB
YAML
203 lines
8.3 KiB
YAML
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z10 -start-before=greedy %s -o - \
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# RUN: | FileCheck %s
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--- |
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define void @f0(double* %ptr1, float* %ptr2) {
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%val0 = load volatile float, float* %ptr2
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%val1 = load volatile float, float* %ptr2
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%val2 = load volatile float, float* %ptr2
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%val3 = load volatile float, float* %ptr2
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%val4 = load volatile float, float* %ptr2
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%val5 = load volatile float, float* %ptr2
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%val6 = load volatile float, float* %ptr2
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%val7 = load volatile float, float* %ptr2
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%val8 = load volatile float, float* %ptr2
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%val9 = load volatile float, float* %ptr2
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%val10 = load volatile float, float* %ptr2
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%val11 = load volatile float, float* %ptr2
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%val12 = load volatile float, float* %ptr2
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%val13 = load volatile float, float* %ptr2
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%val14 = load volatile float, float* %ptr2
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%val15 = load volatile float, float* %ptr2
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%val16 = load volatile float, float* %ptr2
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%ext0 = fpext float %val0 to double
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%ext1 = fpext float %val1 to double
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%ext2 = fpext float %val2 to double
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%ext3 = fpext float %val3 to double
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%ext4 = fpext float %val4 to double
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%ext5 = fpext float %val5 to double
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%ext6 = fpext float %val6 to double
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%ext7 = fpext float %val7 to double
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%ext8 = fpext float %val8 to double
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%ext9 = fpext float %val9 to double
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%ext10 = fpext float %val10 to double
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%ext11 = fpext float %val11 to double
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%ext12 = fpext float %val12 to double
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%ext13 = fpext float %val13 to double
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%ext14 = fpext float %val14 to double
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%ext15 = fpext float %val15 to double
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%ext16 = fpext float %val16 to double
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store volatile float %val0, float* %ptr2
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store volatile float %val1, float* %ptr2
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store volatile float %val2, float* %ptr2
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store volatile float %val3, float* %ptr2
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store volatile float %val4, float* %ptr2
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store volatile float %val5, float* %ptr2
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store volatile float %val6, float* %ptr2
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store volatile float %val7, float* %ptr2
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store volatile float %val8, float* %ptr2
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store volatile float %val9, float* %ptr2
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store volatile float %val10, float* %ptr2
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store volatile float %val11, float* %ptr2
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store volatile float %val12, float* %ptr2
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store volatile float %val13, float* %ptr2
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store volatile float %val14, float* %ptr2
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store volatile float %val15, float* %ptr2
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store volatile float %val16, float* %ptr2
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store volatile double %ext0, double* %ptr1
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store volatile double %ext1, double* %ptr1
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store volatile double %ext2, double* %ptr1
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store volatile double %ext3, double* %ptr1
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store volatile double %ext4, double* %ptr1
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store volatile double %ext5, double* %ptr1
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store volatile double %ext6, double* %ptr1
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store volatile double %ext7, double* %ptr1
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store volatile double %ext8, double* %ptr1
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store volatile double %ext9, double* %ptr1
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store volatile double %ext10, double* %ptr1
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store volatile double %ext11, double* %ptr1
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store volatile double %ext12, double* %ptr1
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store volatile double %ext13, double* %ptr1
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store volatile double %ext14, double* %ptr1
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store volatile double %ext15, double* %ptr1
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store volatile double %ext16, double* %ptr1
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ret void
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}
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...
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# CHECK-LABEL: f0:
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# CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
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# CHECK: br %r14
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---
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name: f0
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: addr64bit }
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- { id: 1, class: addr64bit }
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- { id: 2, class: fp32bit }
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- { id: 3, class: fp32bit }
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- { id: 4, class: fp32bit }
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- { id: 5, class: fp32bit }
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- { id: 6, class: fp32bit }
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- { id: 7, class: fp32bit }
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- { id: 8, class: fp32bit }
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- { id: 9, class: fp32bit }
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- { id: 10, class: fp32bit }
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- { id: 11, class: fp32bit }
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- { id: 12, class: fp32bit }
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- { id: 13, class: fp32bit }
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- { id: 14, class: fp32bit }
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- { id: 15, class: fp32bit }
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- { id: 16, class: fp32bit }
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- { id: 17, class: fp32bit }
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- { id: 18, class: fp32bit }
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- { id: 19, class: fp64bit }
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- { id: 20, class: fp64bit }
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- { id: 21, class: fp64bit }
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- { id: 22, class: fp64bit }
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- { id: 23, class: fp64bit }
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- { id: 24, class: fp64bit }
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- { id: 25, class: fp64bit }
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- { id: 26, class: fp64bit }
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- { id: 27, class: fp64bit }
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- { id: 28, class: fp64bit }
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- { id: 29, class: fp64bit }
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- { id: 30, class: fp64bit }
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- { id: 31, class: fp64bit }
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- { id: 32, class: fp64bit }
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- { id: 33, class: fp64bit }
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- { id: 34, class: fp64bit }
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- { id: 35, class: fp64bit }
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liveins:
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- { reg: '$r2d', virtual-reg: '%0' }
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- { reg: '$r3d', virtual-reg: '%1' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $r2d, $r3d
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%1 = COPY $r3d
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%0 = COPY $r2d
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%2 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%3 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%4 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%5 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%6 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%7 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%8 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%9 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%10 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%11 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%12 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%13 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%14 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%15 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%16 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%17 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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%18 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
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STE %2, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %3, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %4, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %5, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %6, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %7, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %8, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %9, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %10, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %11, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %12, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %13, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %14, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %15, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %16, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %17, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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STE %18, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
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%19 = LDEBR %2, implicit $fpc
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STD %19, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%20 = LDEBR %3, implicit $fpc
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STD %20, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%21 = LDEBR %4, implicit $fpc
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STD %21, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%22 = LDEBR %5, implicit $fpc
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STD %22, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%23 = LDEBR %6, implicit $fpc
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STD %23, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%24 = LDEBR %7, implicit $fpc
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STD %24, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%25 = LDEBR %8, implicit $fpc
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STD %25, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%26 = LDEBR %9, implicit $fpc
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STD %26, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%27 = LDEBR %10, implicit $fpc
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STD %27, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%28 = LDEBR %11, implicit $fpc
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STD %28, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%29 = LDEBR %12, implicit $fpc
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STD %29, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%30 = LDEBR %13, implicit $fpc
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STD %30, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%31 = LDEBR %14, implicit $fpc
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STD %31, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%32 = LDEBR %15, implicit $fpc
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STD %32, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%33 = LDEBR %16, implicit $fpc
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STD %33, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%34 = LDEBR %17, implicit $fpc
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STD %34, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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%35 = LDEBR %18, implicit $fpc
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STD %35, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
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Return
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...
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