0f0a8b7784
This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Assembler/disassembler support for new instructions. - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of arch13 as host processor. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365932
139 lines
4.3 KiB
LLVM
139 lines
4.3 KiB
LLVM
; Test loads of byte-swapped vector elements.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
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; Test v16i8 loads.
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define <16 x i8> @f1(<16 x i8> *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vlbrq %v24, 0(%r2)
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; CHECK: br %r14
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%load = load <16 x i8>, <16 x i8> *%ptr
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%ret = shufflevector <16 x i8> %load, <16 x i8> undef,
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<16 x i32> <i32 15, i32 14, i32 13, i32 12,
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i32 11, i32 10, i32 9, i32 8,
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i32 7, i32 6, i32 5, i32 4,
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i32 3, i32 2, i32 1, i32 0>
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ret <16 x i8> %ret
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}
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; Test v8i16 loads.
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define <8 x i16> @f2(<8 x i16> *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: vlerh %v24, 0(%r2)
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; CHECK: br %r14
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%load = load <8 x i16>, <8 x i16> *%ptr
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%ret = shufflevector <8 x i16> %load, <8 x i16> undef,
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<8 x i32> <i32 7, i32 6, i32 5, i32 4,
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i32 3, i32 2, i32 1, i32 0>
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ret <8 x i16> %ret
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}
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; Test v4i32 loads.
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define <4 x i32> @f3(<4 x i32> *%ptr) {
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; CHECK-LABEL: f3:
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; CHECK: vlerf %v24, 0(%r2)
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; CHECK: br %r14
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%load = load <4 x i32>, <4 x i32> *%ptr
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%ret = shufflevector <4 x i32> %load, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %ret
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}
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; Test v2i64 loads.
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define <2 x i64> @f4(<2 x i64> *%ptr) {
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; CHECK-LABEL: f4:
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; CHECK: vlerg %v24, 0(%r2)
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; CHECK: br %r14
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%load = load <2 x i64>, <2 x i64> *%ptr
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%ret = shufflevector <2 x i64> %load, <2 x i64> undef,
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<2 x i32> <i32 1, i32 0>
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ret <2 x i64> %ret
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}
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; Test v4f32 loads.
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define <4 x float> @f5(<4 x float> *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK: vlerf %v24, 0(%r2)
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; CHECK: br %r14
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%load = load <4 x float>, <4 x float> *%ptr
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%ret = shufflevector <4 x float> %load, <4 x float> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %ret
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}
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; Test v2f64 loads.
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define <2 x double> @f6(<2 x double> *%ptr) {
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; CHECK-LABEL: f6:
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; CHECK: vlerg %v24, 0(%r2)
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; CHECK: br %r14
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%load = load <2 x double>, <2 x double> *%ptr
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%ret = shufflevector <2 x double> %load, <2 x double> undef,
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<2 x i32> <i32 1, i32 0>
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ret <2 x double> %ret
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}
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; Test the highest aligned in-range offset.
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define <4 x i32> @f7(<4 x i32> *%base) {
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; CHECK-LABEL: f7:
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; CHECK: vlerf %v24, 4080(%r2)
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; CHECK: br %r14
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%ptr = getelementptr <4 x i32>, <4 x i32> *%base, i64 255
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%load = load <4 x i32>, <4 x i32> *%ptr
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%ret = shufflevector <4 x i32> %load, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %ret
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}
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; Test the highest unaligned in-range offset.
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define <4 x i32> @f8(i8 *%base) {
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; CHECK-LABEL: f8:
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; CHECK: vlerf %v24, 4095(%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, i8 *%base, i64 4095
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%ptr = bitcast i8 *%addr to <4 x i32> *
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%load = load <4 x i32>, <4 x i32> *%ptr
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%ret = shufflevector <4 x i32> %load, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %ret
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}
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; Test the next offset up, which requires separate address logic,
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define <4 x i32> @f9(<4 x i32> *%base) {
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; CHECK-LABEL: f9:
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; CHECK: aghi %r2, 4096
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; CHECK: vlerf %v24, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr <4 x i32>, <4 x i32> *%base, i64 256
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%load = load <4 x i32>, <4 x i32> *%ptr
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%ret = shufflevector <4 x i32> %load, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %ret
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}
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; Test negative offsets, which also require separate address logic,
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define <4 x i32> @f10(<4 x i32> *%base) {
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; CHECK-LABEL: f10:
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; CHECK: aghi %r2, -16
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; CHECK: vlerf %v24, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr <4 x i32>, <4 x i32> *%base, i64 -1
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%load = load <4 x i32>, <4 x i32> *%ptr
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%ret = shufflevector <4 x i32> %load, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %ret
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}
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; Check that indexes are allowed.
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define <4 x i32> @f11(i8 *%base, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: vlerf %v24, 0(%r3,%r2)
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; CHECK: br %r14
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%addr = getelementptr i8, i8 *%base, i64 %index
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%ptr = bitcast i8 *%addr to <4 x i32> *
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%load = load <4 x i32>, <4 x i32> *%ptr
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%ret = shufflevector <4 x i32> %load, <4 x i32> undef,
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<4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %ret
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}
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