7323c2bf85
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between SETcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: andreadb, courbet, RKSimon, spatel, lebedev.ri Reviewed By: andreadb Subscribers: hiraditya, lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60138 llvm-svn: 357801
487 lines
14 KiB
YAML
487 lines
14 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
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--- |
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define i32 @test_icmp_eq_i8(i8 %a, i8 %b) {
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%r = icmp eq i8 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_eq_i16(i16 %a, i16 %b) {
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%r = icmp eq i16 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_eq_i64(i64 %a, i64 %b) {
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%r = icmp eq i64 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_eq_i32(i32 %a, i32 %b) {
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%r = icmp eq i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_ne_i32(i32 %a, i32 %b) {
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%r = icmp ne i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_ugt_i32(i32 %a, i32 %b) {
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%r = icmp ugt i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_uge_i32(i32 %a, i32 %b) {
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%r = icmp uge i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_ult_i32(i32 %a, i32 %b) {
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%r = icmp ult i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_ule_i32(i32 %a, i32 %b) {
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%r = icmp ule i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_sgt_i32(i32 %a, i32 %b) {
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%r = icmp sgt i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_sge_i32(i32 %a, i32 %b) {
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%r = icmp sge i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_slt_i32(i32 %a, i32 %b) {
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%r = icmp slt i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_icmp_sle_i32(i32 %a, i32 %b) {
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%r = icmp sle i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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...
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---
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name: test_icmp_eq_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_eq_i8
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; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $dil
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; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
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; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s8) = COPY $dil
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%1(s8) = COPY $sil
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%2(s1) = G_ICMP intpred(eq), %0(s8), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_eq_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_eq_i16
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; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $di
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; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si
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; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s16) = COPY $di
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%1(s16) = COPY $si
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%2(s1) = G_ICMP intpred(eq), %0(s16), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_eq_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_icmp_eq_i64
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s1) = G_ICMP intpred(eq), %0(s64), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_eq_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_eq_i32
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s1) = G_ICMP intpred(eq), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_ne_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_ne_i32
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s1) = G_ICMP intpred(ne), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_ugt_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_ugt_i32
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_uge_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_uge_i32
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s1) = G_ICMP intpred(uge), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_ult_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_ult_i32
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s1) = G_ICMP intpred(ult), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_ule_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_ule_i32
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s1) = G_ICMP intpred(ule), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_sgt_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_sgt_i32
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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$eax = COPY %3(s32)
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RET 0, implicit $eax
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...
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---
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name: test_icmp_sge_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_icmp_sge_i32
|
|
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
|
|
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
|
|
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags
|
|
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
|
|
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
|
|
; CHECK: $eax = COPY [[AND32ri8_]]
|
|
; CHECK: RET 0, implicit $eax
|
|
%0(s32) = COPY $edi
|
|
%1(s32) = COPY $esi
|
|
%2(s1) = G_ICMP intpred(sge), %0(s32), %1
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
$eax = COPY %3(s32)
|
|
RET 0, implicit $eax
|
|
|
|
...
|
|
---
|
|
name: test_icmp_slt_i32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
- { id: 3, class: gpr }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi, $esi
|
|
|
|
; CHECK-LABEL: name: test_icmp_slt_i32
|
|
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
|
|
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
|
|
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags
|
|
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
|
|
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
|
|
; CHECK: $eax = COPY [[AND32ri8_]]
|
|
; CHECK: RET 0, implicit $eax
|
|
%0(s32) = COPY $edi
|
|
%1(s32) = COPY $esi
|
|
%2(s1) = G_ICMP intpred(slt), %0(s32), %1
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
$eax = COPY %3(s32)
|
|
RET 0, implicit $eax
|
|
|
|
...
|
|
---
|
|
name: test_icmp_sle_i32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
- { id: 3, class: gpr }
|
|
body: |
|
|
bb.1 (%ir-block.0):
|
|
liveins: $edi, $esi
|
|
|
|
; CHECK-LABEL: name: test_icmp_sle_i32
|
|
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
|
|
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
|
|
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
|
|
; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags
|
|
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETCCr]], %subreg.sub_8bit
|
|
; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags
|
|
; CHECK: $eax = COPY [[AND32ri8_]]
|
|
; CHECK: RET 0, implicit $eax
|
|
%0(s32) = COPY $edi
|
|
%1(s32) = COPY $esi
|
|
%2(s1) = G_ICMP intpred(sle), %0(s32), %1
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
$eax = COPY %3(s32)
|
|
RET 0, implicit $eax
|
|
|
|
...
|