46e5052b8e
INC/DEC is really a special case of a more generic issue. We should also turn leas into add reg/reg or add reg/imm regardless of the slow lea flags. This also supports LEA64_32 which has 64 bit input registers and 32 bit output registers. So we need to convert the 64 bit inputs to their 32 bit equivalents to check if they are equal to base reg. One thing to note, the original code preserved the kill flags by adding operands to the new instruction instead of using addReg. But I think tied operands aren't supposed to have the kill flag set. I dropped the kill flags, but I could probably try to preserve it in the add reg/reg case if we think its important. Not sure which operand its supposed to go on for the LEA64_32r instruction due to the super reg implicit uses. Though I'm also not sure those are needed since they were probably just created by an INSERT_SUBREG from a 32-bit input. Differential Revision: https://reviews.llvm.org/D61472 llvm-svn: 361691
104 lines
2.6 KiB
LLVM
104 lines
2.6 KiB
LLVM
;; X's live range extends beyond the shift, so the register allocator
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;; cannot coalesce it with Y. Because of this, a copy needs to be
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;; emitted before the shift to save the register value before it is
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;; clobbered. However, this copy is not needed if the register
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;; allocator turns the shift into an LEA. This also occurs for ADD.
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; Check that the shift gets turned into an LEA.
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; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin | FileCheck %s
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@G = external global i32
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define i32 @test1(i32 %X) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: movl %edi, %eax
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; CHECK: leal 1(%rax)
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%Z = add i32 %X, 1
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store volatile i32 %Z, i32* @G
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ret i32 %X
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}
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; rdar://8977508
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; The second add should not be transformed to leal nor should it be
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; commutted (which would require inserting a copy).
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define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
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entry:
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; CHECK-LABEL: test2:
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; CHECK: leal
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; CHECK-NEXT: addl
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; CHECK-NEXT: addl
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; CHECK-NEXT: ret
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%add = add i32 %b, %a
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%add3 = add i32 %add, %c
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%add5 = add i32 %add3, %d
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ret i32 %add5
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}
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; rdar://9002648
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define i64 @test3(i64 %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: test3:
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; CHECK: leaq (%rdi,%rdi), %rax
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; CHECK-NOT: addq
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; CHECK-NEXT: ret
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%0 = shl i64 %x, 1
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ret i64 %0
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}
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@global = external global i32, align 4
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@global2 = external global i64, align 8
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; Test that liveness is properly updated and we do not encounter the
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; assert/crash from http://llvm.org/PR28301
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; CHECK-LABEL: ham
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define void @ham() {
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bb:
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br label %bb1
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bb1:
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%tmp = phi i64 [ %tmp40, %bb9 ], [ 0, %bb ]
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%tmp2 = phi i32 [ %tmp39, %bb9 ], [ 0, %bb ]
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%tmp3 = icmp sgt i32 undef, 10
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br i1 %tmp3, label %bb2, label %bb3
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bb2:
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%tmp6 = load i32, i32* @global, align 4
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%tmp8 = add nsw i32 %tmp6, %tmp2
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%tmp9 = sext i32 %tmp8 to i64
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br label %bb6
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bb3:
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; CHECK: subl %e[[REG0:[a-z0-9]+]],
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; CHECK: addq $4, %r[[REG0]]
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%tmp14 = phi i64 [ %tmp15, %bb5 ], [ 0, %bb1 ]
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%tmp15 = add nuw i64 %tmp14, 4
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%tmp16 = trunc i64 %tmp14 to i32
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%tmp17 = sub i32 %tmp2, %tmp16
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br label %bb4
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bb4:
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%tmp20 = phi i64 [ %tmp14, %bb3 ], [ %tmp34, %bb5 ]
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%tmp28 = icmp eq i32 %tmp17, 0
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br i1 %tmp28, label %bb5, label %bb8
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bb5:
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%tmp34 = add nuw nsw i64 %tmp20, 1
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%tmp35 = icmp slt i64 %tmp34, %tmp15
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br i1 %tmp35, label %bb4, label %bb3
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bb6:
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store volatile i64 %tmp, i64* @global2, align 8
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store volatile i64 %tmp9, i64* @global2, align 8
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store volatile i32 %tmp6, i32* @global, align 4
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%tmp45 = icmp slt i32 undef, undef
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br i1 %tmp45, label %bb6, label %bb9
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bb8:
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unreachable
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bb9:
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%tmp39 = add nuw nsw i32 %tmp2, 4
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%tmp40 = add nuw i64 %tmp, 4
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br label %bb1
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}
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