Eli Friedman 5df3a87224 [AArch64][X86] Don't assume __powidf2 is available on Windows. ...

We had some code for this for 32-bit ARM, but this doesn't really need
to be in target-specific code; generalize it.

(I think this started showing up recently because we added an
optimization that converts pow to powi.)

Differential Revision: https://reviews.llvm.org/D69013

2019-11-08 12:43:21 -08:00

..

CMakeLists.txt

…

DAGCombiner.cpp

[X86/Atomics] Correct a few transforms for new atomic lowering

2019-11-05 13:20:08 -08:00

FastISel.cpp

FastISel - fix uninitialized variable warnings in constructor. NFCI.

2019-11-02 18:03:22 +00:00

FunctionLoweringInfo.cpp

Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each

2019-10-19 01:31:09 +00:00

InstrEmitter.cpp

[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field

2019-10-15 10:46:24 +00:00

InstrEmitter.h

[SelectionDAG] Enhance the simplification of copyto from implicit-def.

2019-05-27 18:26:29 +00:00

LegalizeDAG.cpp

[AArch64][X86] Don't assume __powidf2 is available on Windows.

2019-11-08 12:43:21 -08:00

LegalizeFloatTypes.cpp

[AArch64][X86] Don't assume __powidf2 is available on Windows.

2019-11-08 12:43:21 -08:00

LegalizeIntegerTypes.cpp

[SelectionDAG] Enable lowering unordered atomics loads w/LoadSDNode (and stores w/StoreSDNode) by default

2019-10-29 12:46:24 -07:00

LegalizeTypes.cpp

[LegalizeTypes] Remove code for softening a float type to itself.

2019-09-12 05:55:14 +00:00

LegalizeTypes.h

[Codegen][ARM] Add float softening for cbrt

2019-10-28 11:08:55 +00:00

LegalizeTypesGeneric.cpp

[SelectionDAG] Enable lowering unordered atomics loads w/LoadSDNode (and stores w/StoreSDNode) by default

2019-10-29 12:46:24 -07:00

LegalizeVectorOps.cpp

Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each

2019-10-19 01:31:09 +00:00

LegalizeVectorTypes.cpp

[SelectionDAG] Add support for FP_ROUND in WidenVectorOperand.

2019-10-30 15:18:21 +00:00

LLVMBuild.txt

…

ResourcePriorityQueue.cpp

Implementation of asm-goto support in LLVM

2019-02-08 20:48:56 +00:00

ScheduleDAGFast.cpp

Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

2019-08-01 23:27:28 +00:00

ScheduleDAGRRList.cpp

[ScheduleDAG] When a node is cloned, add an edge between the nodes.

2019-10-04 19:51:40 +00:00

ScheduleDAGSDNodes.cpp

Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs"

2019-10-28 16:59:32 -07:00

ScheduleDAGSDNodes.h

Prune Analysis includes from SelectionDAG.h

2019-10-19 01:07:48 +00:00

ScheduleDAGVLIW.cpp

Prune Analysis includes from SelectionDAG.h

2019-10-19 01:07:48 +00:00

SDNodeDbgValue.h

…

SelectionDAG.cpp

Fix uninitialized variable warning. NFCI.

2019-11-02 14:42:38 +00:00

SelectionDAGAddressAnalysis.cpp

Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each

2019-10-19 01:31:09 +00:00

SelectionDAGBuilder.cpp

[IR] Add Freeze instruction

2019-11-05 15:54:56 +09:00

SelectionDAGBuilder.h

[IR] Add Freeze instruction

2019-11-05 15:54:56 +09:00

SelectionDAGDumper.cpp

[AArch64][SVE] Add SPLAT_VECTOR ISD Node

2019-10-18 11:48:35 +00:00

SelectionDAGISel.cpp

[SelectionDAG] Fixed null check after dereferencing warning. NFCI.

2019-11-03 19:34:03 +01:00

SelectionDAGPrinter.cpp

…

SelectionDAGTargetInfo.cpp

…

StatepointLowering.cpp

[Statepoints] Fix overalignment of loads in no-realign-stack functions

2019-08-02 20:17:37 +00:00

StatepointLowering.h

[FastISel] Fix crash for gc.relocate lowring

2019-04-05 05:41:08 +00:00

TargetLowering.cpp

[SDAG] reduce code duplication; NFC

2019-11-07 10:28:45 -05:00