ced0d1f42b
Currently, bpf does not specify 128bit alignment in its
layout spec. So for a structure like
struct ipv6_key_t {
unsigned pid;
unsigned __int128 saddr;
unsigned short lport;
};
clang will generate IR type
%struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] }
Additional padding is to ensure later IR->MIR can generate correct
stack layout with target layout spec.
But it is common practice for a tracing program to be
first compiled with target flag (e.g., x86_64 or aarch64) through
clang to generate IR and then go through llc to generate bpf
byte code. Tracing program often refers to kernel internal
data structures which needs to be compiled with non-bpf target.
But such a compilation model may cause a problem on aarch64.
The bcc issue https://github.com/iovisor/bcc/issues/2827
reported such a problem.
For the above structure, since aarch64 has "i128:128" in its
layout string, the generated IR will have
%struct.ipv6_key_t = type { i32, i128, i16 }
Since bpf does not have "i128:128" in its spec string,
the selectionDAG assumes alignment 8 for i128 and
computes the stack storage size for the above is 32 bytes,
which leads incorrect code later.
The x86_64 does not have this issue as it does not have
"i128:128" in its layout spec as it does permits i128 to
be alignmented at 8 bytes at stack. Its IR type looks like
%struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] }
The fix here is add i128 support in layout spec, the same as
aarch64. The only downside is we may have less optimal stack
allocation in certain cases since we require 16byte alignment
for i128 instead of 8. But this is probably fine as i128 is
not used widely and in most cases users should already
have proper alignment.
Differential Revision: https://reviews.llvm.org/D76587
132 lines
4.4 KiB
C++
132 lines
4.4 KiB
C++
//===-- BPFTargetMachine.cpp - Define TargetMachine for BPF ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about BPF target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "BPFTargetMachine.h"
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#include "BPF.h"
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#include "MCTargetDesc/BPFMCAsmInfo.h"
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#include "TargetInfo/BPFTargetInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::
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opt<bool> DisableMIPeephole("disable-bpf-peephole", cl::Hidden,
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cl::desc("Disable machine peepholes for BPF"));
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFTarget() {
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// Register the target.
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RegisterTargetMachine<BPFTargetMachine> X(getTheBPFleTarget());
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RegisterTargetMachine<BPFTargetMachine> Y(getTheBPFbeTarget());
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RegisterTargetMachine<BPFTargetMachine> Z(getTheBPFTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeBPFAbstractMemberAccessPass(PR);
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initializeBPFMIPeepholePass(PR);
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initializeBPFMIPeepholeTruncElimPass(PR);
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}
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// DataLayout: little or big endian
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static std::string computeDataLayout(const Triple &TT) {
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if (TT.getArch() == Triple::bpfeb)
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return "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
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else
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return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::PIC_;
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return *RM;
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}
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BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
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Subtarget(TT, std::string(CPU), std::string(FS), *this) {
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initAsmInfo();
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BPFMCAsmInfo *MAI =
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static_cast<BPFMCAsmInfo *>(const_cast<MCAsmInfo *>(AsmInfo.get()));
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MAI->setDwarfUsesRelocationsAcrossSections(!Subtarget.getUseDwarfRIS());
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}
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namespace {
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// BPF Code Generator Pass Configuration Options.
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class BPFPassConfig : public TargetPassConfig {
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public:
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BPFPassConfig(BPFTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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BPFTargetMachine &getBPFTargetMachine() const {
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return getTM<BPFTargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addMachineSSAOptimization() override;
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void addPreEmitPass() override;
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};
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}
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TargetPassConfig *BPFTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new BPFPassConfig(*this, PM);
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}
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void BPFPassConfig::addIRPasses() {
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addPass(createBPFAbstractMemberAccess(&getBPFTargetMachine()));
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TargetPassConfig::addIRPasses();
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}
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// Install an instruction selector pass using
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// the ISelDag to gen BPF code.
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bool BPFPassConfig::addInstSelector() {
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addPass(createBPFISelDag(getBPFTargetMachine()));
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return false;
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}
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void BPFPassConfig::addMachineSSAOptimization() {
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addPass(createBPFMISimplifyPatchablePass());
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// The default implementation must be called first as we want eBPF
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// Peephole ran at last.
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TargetPassConfig::addMachineSSAOptimization();
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const BPFSubtarget *Subtarget = getBPFTargetMachine().getSubtargetImpl();
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if (!DisableMIPeephole) {
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if (Subtarget->getHasAlu32())
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addPass(createBPFMIPeepholePass());
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addPass(createBPFMIPeepholeTruncElimPass());
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}
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}
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void BPFPassConfig::addPreEmitPass() {
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addPass(createBPFMIPreEmitCheckingPass());
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if (getOptLevel() != CodeGenOpt::None)
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if (!DisableMIPeephole)
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addPass(createBPFMIPreEmitPeepholePass());
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}
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