ca9ba76481
Summary: Extends the multivalue call infrastructure to tail calls, removes all legacy calls specialized for particular result types, and removes the CallIndirectFixup pass, since all indirect call arguments are now fixed up directly in the post-insertion hook. In order to keep supporting pretty-printed defs and uses in test expectations, MCInstLower now inserts an immediate containing the number of defs for each call and call_indirect. The InstPrinter is updated to query this immediate if it is present and determine which MCOperands are defs and uses accordingly. Depends on D72902. Reviewers: aheejin Subscribers: dschuff, mgorny, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74192
490 lines
16 KiB
C++
490 lines
16 KiB
C++
//==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file provides WebAssembly-specific target descriptions.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
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#include "../WebAssemblySubtarget.h"
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#include "llvm/BinaryFormat/Wasm.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/DataTypes.h"
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#include <memory>
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class MCSubtargetInfo;
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class MVT;
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class Target;
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class Triple;
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class raw_pwrite_stream;
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MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
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MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
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std::unique_ptr<MCObjectTargetWriter>
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createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten);
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namespace WebAssembly {
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enum OperandType {
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/// Basic block label in a branch construct.
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OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
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/// Local index.
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OPERAND_LOCAL,
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/// Global index.
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OPERAND_GLOBAL,
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/// 32-bit integer immediates.
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OPERAND_I32IMM,
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/// 64-bit integer immediates.
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OPERAND_I64IMM,
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/// 32-bit floating-point immediates.
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OPERAND_F32IMM,
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/// 64-bit floating-point immediates.
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OPERAND_F64IMM,
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/// 8-bit vector lane immediate
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OPERAND_VEC_I8IMM,
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/// 16-bit vector lane immediate
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OPERAND_VEC_I16IMM,
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/// 32-bit vector lane immediate
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OPERAND_VEC_I32IMM,
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/// 64-bit vector lane immediate
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OPERAND_VEC_I64IMM,
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/// 32-bit unsigned function indices.
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OPERAND_FUNCTION32,
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/// 32-bit unsigned memory offsets.
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OPERAND_OFFSET32,
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/// p2align immediate for load and store address alignment.
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OPERAND_P2ALIGN,
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/// signature immediate for block/loop.
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OPERAND_SIGNATURE,
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/// type signature immediate for call_indirect.
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OPERAND_TYPEINDEX,
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/// Event index.
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OPERAND_EVENT,
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/// A list of branch targets for br_list.
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OPERAND_BRLIST,
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};
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} // end namespace WebAssembly
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namespace WebAssemblyII {
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/// Target Operand Flag enum.
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enum TOF {
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MO_NO_FLAG = 0,
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// On a symbol operand this indicates that the immediate is a wasm global
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// index. The value of the wasm global will be set to the symbol address at
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// runtime. This adds a level of indirection similar to the GOT on native
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// platforms.
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MO_GOT,
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// On a symbol operand this indicates that the immediate is the symbol
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// address relative the __memory_base wasm global.
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// Only applicable to data symbols.
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MO_MEMORY_BASE_REL,
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// On a symbol operand this indicates that the immediate is the symbol
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// address relative the __table_base wasm global.
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// Only applicable to function symbols.
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MO_TABLE_BASE_REL,
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};
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} // end namespace WebAssemblyII
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} // end namespace llvm
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// Defines symbolic names for WebAssembly registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "WebAssemblyGenRegisterInfo.inc"
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// Defines symbolic names for the WebAssembly instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "WebAssemblyGenInstrInfo.inc"
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namespace llvm {
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namespace WebAssembly {
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/// Used as immediate MachineOperands for block signatures
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enum class BlockType : unsigned {
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Invalid = 0x00,
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Void = 0x40,
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I32 = unsigned(wasm::ValType::I32),
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I64 = unsigned(wasm::ValType::I64),
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F32 = unsigned(wasm::ValType::F32),
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F64 = unsigned(wasm::ValType::F64),
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V128 = unsigned(wasm::ValType::V128),
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Exnref = unsigned(wasm::ValType::EXNREF),
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// Multivalue blocks (and other non-void blocks) are only emitted when the
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// blocks will never be exited and are at the ends of functions (see
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// WebAssemblyCFGStackify::fixEndsAtEndOfFunction). They also are never made
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// to pop values off the stack, so the exact multivalue signature can always
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// be inferred from the return type of the parent function in MCInstLower.
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Multivalue = 0xffff,
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};
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/// Instruction opcodes emitted via means other than CodeGen.
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static const unsigned Nop = 0x01;
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static const unsigned End = 0x0b;
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wasm::ValType toValType(const MVT &Ty);
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/// Return the default p2align value for a load or store with the given opcode.
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inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::LOAD8_S_I32:
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case WebAssembly::LOAD8_S_I32_S:
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case WebAssembly::LOAD8_U_I32:
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case WebAssembly::LOAD8_U_I32_S:
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case WebAssembly::LOAD8_S_I64:
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case WebAssembly::LOAD8_S_I64_S:
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case WebAssembly::LOAD8_U_I64:
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case WebAssembly::LOAD8_U_I64_S:
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case WebAssembly::ATOMIC_LOAD8_U_I32:
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case WebAssembly::ATOMIC_LOAD8_U_I32_S:
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case WebAssembly::ATOMIC_LOAD8_U_I64:
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case WebAssembly::ATOMIC_LOAD8_U_I64_S:
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case WebAssembly::STORE8_I32:
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case WebAssembly::STORE8_I32_S:
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case WebAssembly::STORE8_I64:
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case WebAssembly::STORE8_I64_S:
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case WebAssembly::ATOMIC_STORE8_I32:
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case WebAssembly::ATOMIC_STORE8_I32_S:
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case WebAssembly::ATOMIC_STORE8_I64:
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case WebAssembly::ATOMIC_STORE8_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_AND_I32:
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case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_AND_I64:
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case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_OR_I32:
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case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_OR_I64:
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case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
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case WebAssembly::LOAD_SPLAT_v8x16:
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case WebAssembly::LOAD_SPLAT_v8x16_S:
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return 0;
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case WebAssembly::LOAD16_S_I32:
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case WebAssembly::LOAD16_S_I32_S:
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case WebAssembly::LOAD16_U_I32:
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case WebAssembly::LOAD16_U_I32_S:
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case WebAssembly::LOAD16_S_I64:
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case WebAssembly::LOAD16_S_I64_S:
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case WebAssembly::LOAD16_U_I64:
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case WebAssembly::LOAD16_U_I64_S:
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case WebAssembly::ATOMIC_LOAD16_U_I32:
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case WebAssembly::ATOMIC_LOAD16_U_I32_S:
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case WebAssembly::ATOMIC_LOAD16_U_I64:
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case WebAssembly::ATOMIC_LOAD16_U_I64_S:
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case WebAssembly::STORE16_I32:
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case WebAssembly::STORE16_I32_S:
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case WebAssembly::STORE16_I64:
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case WebAssembly::STORE16_I64_S:
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case WebAssembly::ATOMIC_STORE16_I32:
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case WebAssembly::ATOMIC_STORE16_I32_S:
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case WebAssembly::ATOMIC_STORE16_I64:
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case WebAssembly::ATOMIC_STORE16_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_AND_I32:
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case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_AND_I64:
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case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_OR_I32:
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case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_OR_I64:
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case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
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case WebAssembly::LOAD_SPLAT_v16x8:
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case WebAssembly::LOAD_SPLAT_v16x8_S:
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return 1;
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case WebAssembly::LOAD_I32:
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case WebAssembly::LOAD_I32_S:
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case WebAssembly::LOAD_F32:
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case WebAssembly::LOAD_F32_S:
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case WebAssembly::STORE_I32:
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case WebAssembly::STORE_I32_S:
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case WebAssembly::STORE_F32:
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case WebAssembly::STORE_F32_S:
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case WebAssembly::LOAD32_S_I64:
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case WebAssembly::LOAD32_S_I64_S:
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case WebAssembly::LOAD32_U_I64:
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case WebAssembly::LOAD32_U_I64_S:
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case WebAssembly::STORE32_I64:
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case WebAssembly::STORE32_I64_S:
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case WebAssembly::ATOMIC_LOAD_I32:
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case WebAssembly::ATOMIC_LOAD_I32_S:
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case WebAssembly::ATOMIC_LOAD32_U_I64:
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case WebAssembly::ATOMIC_LOAD32_U_I64_S:
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case WebAssembly::ATOMIC_STORE_I32:
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case WebAssembly::ATOMIC_STORE_I32_S:
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case WebAssembly::ATOMIC_STORE32_I64:
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case WebAssembly::ATOMIC_STORE32_I64_S:
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case WebAssembly::ATOMIC_RMW_ADD_I32:
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case WebAssembly::ATOMIC_RMW_ADD_I32_S:
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case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
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case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
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case WebAssembly::ATOMIC_RMW_SUB_I32:
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case WebAssembly::ATOMIC_RMW_SUB_I32_S:
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case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
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case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
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case WebAssembly::ATOMIC_RMW_AND_I32:
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case WebAssembly::ATOMIC_RMW_AND_I32_S:
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case WebAssembly::ATOMIC_RMW32_U_AND_I64:
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case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
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case WebAssembly::ATOMIC_RMW_OR_I32:
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case WebAssembly::ATOMIC_RMW_OR_I32_S:
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case WebAssembly::ATOMIC_RMW32_U_OR_I64:
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case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
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case WebAssembly::ATOMIC_RMW_XOR_I32:
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case WebAssembly::ATOMIC_RMW_XOR_I32_S:
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case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
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case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
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case WebAssembly::ATOMIC_RMW_XCHG_I32:
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case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
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case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
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case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
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case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
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case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
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case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
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case WebAssembly::ATOMIC_NOTIFY:
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case WebAssembly::ATOMIC_NOTIFY_S:
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case WebAssembly::ATOMIC_WAIT_I32:
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case WebAssembly::ATOMIC_WAIT_I32_S:
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case WebAssembly::LOAD_SPLAT_v32x4:
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case WebAssembly::LOAD_SPLAT_v32x4_S:
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return 2;
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case WebAssembly::LOAD_I64:
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case WebAssembly::LOAD_I64_S:
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case WebAssembly::LOAD_F64:
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case WebAssembly::LOAD_F64_S:
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case WebAssembly::STORE_I64:
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case WebAssembly::STORE_I64_S:
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case WebAssembly::STORE_F64:
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case WebAssembly::STORE_F64_S:
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case WebAssembly::ATOMIC_LOAD_I64:
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case WebAssembly::ATOMIC_LOAD_I64_S:
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case WebAssembly::ATOMIC_STORE_I64:
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case WebAssembly::ATOMIC_STORE_I64_S:
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case WebAssembly::ATOMIC_RMW_ADD_I64:
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case WebAssembly::ATOMIC_RMW_ADD_I64_S:
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case WebAssembly::ATOMIC_RMW_SUB_I64:
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case WebAssembly::ATOMIC_RMW_SUB_I64_S:
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case WebAssembly::ATOMIC_RMW_AND_I64:
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case WebAssembly::ATOMIC_RMW_AND_I64_S:
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case WebAssembly::ATOMIC_RMW_OR_I64:
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case WebAssembly::ATOMIC_RMW_OR_I64_S:
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case WebAssembly::ATOMIC_RMW_XOR_I64:
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case WebAssembly::ATOMIC_RMW_XOR_I64_S:
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case WebAssembly::ATOMIC_RMW_XCHG_I64:
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case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
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case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
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case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
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case WebAssembly::ATOMIC_WAIT_I64:
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case WebAssembly::ATOMIC_WAIT_I64_S:
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case WebAssembly::LOAD_SPLAT_v64x2:
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case WebAssembly::LOAD_SPLAT_v64x2_S:
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case WebAssembly::LOAD_EXTEND_S_v8i16:
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case WebAssembly::LOAD_EXTEND_S_v8i16_S:
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case WebAssembly::LOAD_EXTEND_U_v8i16:
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case WebAssembly::LOAD_EXTEND_U_v8i16_S:
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case WebAssembly::LOAD_EXTEND_S_v4i32:
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case WebAssembly::LOAD_EXTEND_S_v4i32_S:
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case WebAssembly::LOAD_EXTEND_U_v4i32:
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case WebAssembly::LOAD_EXTEND_U_v4i32_S:
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case WebAssembly::LOAD_EXTEND_S_v2i64:
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case WebAssembly::LOAD_EXTEND_S_v2i64_S:
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case WebAssembly::LOAD_EXTEND_U_v2i64:
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case WebAssembly::LOAD_EXTEND_U_v2i64_S:
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return 3;
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case WebAssembly::LOAD_V128:
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case WebAssembly::LOAD_V128_S:
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case WebAssembly::STORE_V128:
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case WebAssembly::STORE_V128_S:
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return 4;
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default:
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return -1;
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}
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}
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inline unsigned GetDefaultP2Align(unsigned Opc) {
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auto Align = GetDefaultP2AlignAny(Opc);
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if (Align == -1U) {
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llvm_unreachable("Only loads and stores have p2align values");
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}
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return Align;
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}
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inline bool isArgument(unsigned Opc) {
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switch (Opc) {
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case WebAssembly::ARGUMENT_i32:
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case WebAssembly::ARGUMENT_i32_S:
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case WebAssembly::ARGUMENT_i64:
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case WebAssembly::ARGUMENT_i64_S:
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case WebAssembly::ARGUMENT_f32:
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case WebAssembly::ARGUMENT_f32_S:
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case WebAssembly::ARGUMENT_f64:
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case WebAssembly::ARGUMENT_f64_S:
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case WebAssembly::ARGUMENT_v16i8:
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case WebAssembly::ARGUMENT_v16i8_S:
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case WebAssembly::ARGUMENT_v8i16:
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case WebAssembly::ARGUMENT_v8i16_S:
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case WebAssembly::ARGUMENT_v4i32:
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case WebAssembly::ARGUMENT_v4i32_S:
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case WebAssembly::ARGUMENT_v2i64:
|
|
case WebAssembly::ARGUMENT_v2i64_S:
|
|
case WebAssembly::ARGUMENT_v4f32:
|
|
case WebAssembly::ARGUMENT_v4f32_S:
|
|
case WebAssembly::ARGUMENT_v2f64:
|
|
case WebAssembly::ARGUMENT_v2f64_S:
|
|
case WebAssembly::ARGUMENT_exnref:
|
|
case WebAssembly::ARGUMENT_exnref_S:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
inline bool isCopy(unsigned Opc) {
|
|
switch (Opc) {
|
|
case WebAssembly::COPY_I32:
|
|
case WebAssembly::COPY_I32_S:
|
|
case WebAssembly::COPY_I64:
|
|
case WebAssembly::COPY_I64_S:
|
|
case WebAssembly::COPY_F32:
|
|
case WebAssembly::COPY_F32_S:
|
|
case WebAssembly::COPY_F64:
|
|
case WebAssembly::COPY_F64_S:
|
|
case WebAssembly::COPY_V128:
|
|
case WebAssembly::COPY_V128_S:
|
|
case WebAssembly::COPY_EXNREF:
|
|
case WebAssembly::COPY_EXNREF_S:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
inline bool isTee(unsigned Opc) {
|
|
switch (Opc) {
|
|
case WebAssembly::TEE_I32:
|
|
case WebAssembly::TEE_I32_S:
|
|
case WebAssembly::TEE_I64:
|
|
case WebAssembly::TEE_I64_S:
|
|
case WebAssembly::TEE_F32:
|
|
case WebAssembly::TEE_F32_S:
|
|
case WebAssembly::TEE_F64:
|
|
case WebAssembly::TEE_F64_S:
|
|
case WebAssembly::TEE_V128:
|
|
case WebAssembly::TEE_V128_S:
|
|
case WebAssembly::TEE_EXNREF:
|
|
case WebAssembly::TEE_EXNREF_S:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
inline bool isCallDirect(unsigned Opc) {
|
|
switch (Opc) {
|
|
case WebAssembly::CALL:
|
|
case WebAssembly::CALL_S:
|
|
case WebAssembly::RET_CALL:
|
|
case WebAssembly::RET_CALL_S:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
inline bool isCallIndirect(unsigned Opc) {
|
|
switch (Opc) {
|
|
case WebAssembly::CALL_INDIRECT:
|
|
case WebAssembly::CALL_INDIRECT_S:
|
|
case WebAssembly::RET_CALL_INDIRECT:
|
|
case WebAssembly::RET_CALL_INDIRECT_S:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
inline bool isMarker(unsigned Opc) {
|
|
switch (Opc) {
|
|
case WebAssembly::BLOCK:
|
|
case WebAssembly::BLOCK_S:
|
|
case WebAssembly::END_BLOCK:
|
|
case WebAssembly::END_BLOCK_S:
|
|
case WebAssembly::LOOP:
|
|
case WebAssembly::LOOP_S:
|
|
case WebAssembly::END_LOOP:
|
|
case WebAssembly::END_LOOP_S:
|
|
case WebAssembly::TRY:
|
|
case WebAssembly::TRY_S:
|
|
case WebAssembly::END_TRY:
|
|
case WebAssembly::END_TRY_S:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
} // end namespace WebAssembly
|
|
} // end namespace llvm
|
|
|
|
#endif
|