043ed2e22a
We should try the generated matchers before the manual selection. This means the patterns are now handling the common cases, but the manual selection code is not yet dead. It's still handling the non-s32/s64 cases (like v2s16 and v2s32). Currently tablegen doesn't have a nice way to have a single pattern that covers multiple types.
133 lines
5.9 KiB
YAML
133 lines
5.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
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---
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name: or_s32_sgpr_sgpr_sgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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; GFX8-LABEL: name: or_s32_sgpr_sgpr_sgpr
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; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
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; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def $scc
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; GFX8: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_OR_B32_]], [[COPY2]], implicit-def $scc
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; GFX8: S_ENDPGM 0, implicit [[S_OR_B32_1]]
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; GFX9-LABEL: name: or_s32_sgpr_sgpr_sgpr
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; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def $scc
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; GFX9: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_OR_B32_]], [[COPY2]], implicit-def $scc
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; GFX9: S_ENDPGM 0, implicit [[S_OR_B32_1]]
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; GFX10-LABEL: name: or_s32_sgpr_sgpr_sgpr
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; GFX10: liveins: $sgpr0, $sgpr1, $sgpr2
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; GFX10: $vcc_hi = IMPLICIT_DEF
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; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; GFX10: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def $scc
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; GFX10: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_OR_B32_]], [[COPY2]], implicit-def $scc
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; GFX10: S_ENDPGM 0, implicit [[S_OR_B32_1]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = COPY $sgpr2
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%3:sgpr(s32) = G_OR %0, %1
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%4:sgpr(s32) = G_OR %3, %2
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S_ENDPGM 0, implicit %4
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...
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---
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name: or_s32_vgpr_vgpr_vgpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX8-LABEL: name: or_s32_vgpr_vgpr_vgpr
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; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GFX8: [[V_OR_B32_e64_1:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_]], [[COPY2]], implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_1]]
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; GFX9-LABEL: name: or_s32_vgpr_vgpr_vgpr
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; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX9: [[V_OR3_B32_:%[0-9]+]]:vgpr_32 = V_OR3_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
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; GFX9: S_ENDPGM 0, implicit [[V_OR3_B32_]]
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; GFX10-LABEL: name: or_s32_vgpr_vgpr_vgpr
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; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX10: $vcc_hi = IMPLICIT_DEF
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; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX10: [[V_OR3_B32_:%[0-9]+]]:vgpr_32 = V_OR3_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
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; GFX10: S_ENDPGM 0, implicit [[V_OR3_B32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s32) = G_OR %0, %1
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%4:vgpr(s32) = G_OR %3, %2
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S_ENDPGM 0, implicit %4
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...
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---
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name: or_s32_vgpr_vgpr_vgpr_multi_use
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX8-LABEL: name: or_s32_vgpr_vgpr_vgpr_multi_use
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; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GFX8: [[V_OR_B32_e64_1:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_]], [[COPY2]], implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_1]], implicit [[V_OR_B32_e64_]]
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; GFX9-LABEL: name: or_s32_vgpr_vgpr_vgpr_multi_use
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; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX9: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GFX9: [[V_OR_B32_e64_1:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_]], [[COPY2]], implicit $exec
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; GFX9: S_ENDPGM 0, implicit [[V_OR_B32_e64_1]], implicit [[V_OR_B32_e64_]]
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; GFX10-LABEL: name: or_s32_vgpr_vgpr_vgpr_multi_use
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; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX10: $vcc_hi = IMPLICIT_DEF
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; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX10: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GFX10: [[V_OR_B32_e64_1:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_OR_B32_e64_]], [[COPY2]], implicit $exec
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; GFX10: S_ENDPGM 0, implicit [[V_OR_B32_e64_1]], implicit [[V_OR_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s32) = G_OR %0, %1
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%4:vgpr(s32) = G_OR %3, %2
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S_ENDPGM 0, implicit %4, implicit %3
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...
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