60b1967c39
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
120 lines
4.5 KiB
YAML
120 lines
4.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=si-optimize-exec-masking-pre-ra -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# Check for regression from assuming an instruction was a copy after
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# dropping the opcode check.
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---
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name: exec_src1_is_not_copy
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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frameOffsetReg: '$sgpr101'
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body: |
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; GCN-LABEL: name: exec_src1_is_not_copy
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[DEF]], implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
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; GCN: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
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; GCN: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY1]], implicit-def dead $scc
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; GCN: $exec = S_MOV_B64_term [[S_AND_B64_]]
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; GCN: SI_MASK_BRANCH %bb.2, implicit $exec
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; GCN: S_BRANCH %bb.1
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; GCN: bb.1:
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; GCN: successors: %bb.2(0x80000000)
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; GCN: bb.2:
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; GCN: successors: %bb.3(0x40000000), %bb.6(0x40000000)
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; GCN: [[S_OR_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_OR_SAVEEXEC_B64 [[S_XOR_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
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; GCN: $exec = S_AND_B64 $exec, [[COPY]], implicit-def dead $scc
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; GCN: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[S_OR_SAVEEXEC_B64_]], implicit-def $scc
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; GCN: $exec = S_XOR_B64_term $exec, [[S_AND_B64_1]], implicit-def $scc
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; GCN: SI_MASK_BRANCH %bb.6, implicit $exec
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; GCN: S_BRANCH %bb.3
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; GCN: bb.3:
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; GCN: successors: %bb.4(0x40000000), %bb.5(0x40000000)
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; GCN: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[DEF]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
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; GCN: [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
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; GCN: $exec = S_MOV_B64_term [[S_AND_B64_2]]
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; GCN: SI_MASK_BRANCH %bb.5, implicit $exec
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; GCN: S_BRANCH %bb.4
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; GCN: bb.4:
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; GCN: successors: %bb.5(0x80000000)
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; GCN: bb.5:
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; GCN: successors: %bb.6(0x80000000)
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; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
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; GCN: bb.6:
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; GCN: $exec = S_OR_B64 $exec, [[S_AND_B64_1]], implicit-def $scc
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $vgpr0
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%0:sreg_64 = COPY $exec
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%1:vgpr_32 = IMPLICIT_DEF
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%2:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
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%3:sreg_64 = COPY $exec, implicit-def $exec
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%4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
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%5:sreg_64 = S_XOR_B64 %4, %3, implicit-def dead $scc
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$exec = S_MOV_B64_term %4
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SI_MASK_BRANCH %bb.2, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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bb.2:
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successors: %bb.3, %bb.6
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%6:sreg_64 = S_OR_SAVEEXEC_B64 %5, implicit-def $exec, implicit-def $scc, implicit $exec
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$exec = S_AND_B64 $exec, %0, implicit-def dead $scc
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%7:sreg_64 = S_AND_B64 $exec, %6, implicit-def $scc
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$exec = S_XOR_B64_term $exec, %7, implicit-def $scc
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SI_MASK_BRANCH %bb.6, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.4, %bb.5
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%8:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
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%9:sreg_64 = COPY $exec, implicit-def $exec
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%10:sreg_64 = S_AND_B64 %9, %8, implicit-def dead $scc
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$exec = S_MOV_B64_term %10
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SI_MASK_BRANCH %bb.5, implicit $exec
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S_BRANCH %bb.4
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bb.4:
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bb.5:
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$exec = S_OR_B64 $exec, %9, implicit-def $scc
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bb.6:
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$exec = S_OR_B64 $exec, %7, implicit-def $scc
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...
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# When folding a v_cndmask and a v_cmp in a pattern leading to
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# s_cbranch_vccz, ensure that an undef operand is handled correctly.
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---
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name: cndmask_cmp_cbranch_fold_undef
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: cndmask_cmp_cbranch_fold_undef
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def $scc
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; GCN: S_CBRANCH_VCCZ %bb.1, implicit $vcc
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; GCN: bb.1:
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bb.0:
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%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0:sreg_64_xexec, implicit $exec
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V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
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$vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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S_CBRANCH_VCCZ %bb.1, implicit $vcc
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bb.1:
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...
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