60b1967c39
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
109 lines
5.9 KiB
LLVM
109 lines
5.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX908,A2V %s
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; RUN: llc -march=amdgcn -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX908,A2M %s
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; GCN-LABEL: {{^}}max_24regs_32a_used:
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; A2V-NOT: SCRATCH_RSRC
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; GFX908-DAG: v_accvgpr_read_b32 v[[VSPILL:[0-9]+]], a0
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; A2M: buffer_store_dword v[[VSPILL]], off, s[{{[0-9:]+}}], 0 offset:[[FI:[0-9]+]] ; 4-byte Folded Spill
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; A2M: buffer_load_dword v[[VSPILL:[0-9]+]], off, s[{{[0-9:]+}}], 0 offset:[[FI]] ; 4-byte Folded Reload
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; GFX908: v_accvgpr_write_b32 a{{[0-9]+}}, v[[VSPILL]]
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; A2V: ScratchSize: 0
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define amdgpu_kernel void @max_24regs_32a_used(<16 x float> addrspace(1)* %arg, float addrspace(1)* %out) #0 {
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bb:
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%in.1 = load <16 x float>, <16 x float> addrspace(1)* %arg
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%mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float 1.0, float 1.0, <16 x float> %in.1, i32 0, i32 0, i32 0)
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%mai.2 = tail call <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float 1.0, float 1.0, <16 x float> %mai.1, i32 0, i32 0, i32 0)
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%elt1 = extractelement <16 x float> %mai.2, i32 0
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%elt2 = extractelement <16 x float> %mai.1, i32 15
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%elt3 = extractelement <16 x float> %mai.1, i32 14
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%elt4 = extractelement <16 x float> %mai.2, i32 1
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store float %elt1, float addrspace(1)* %out
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%gep1 = getelementptr float, float addrspace(1)* %out, i64 1
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store float %elt2, float addrspace(1)* %gep1
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%gep2 = getelementptr float, float addrspace(1)* %out, i64 2
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store float %elt3, float addrspace(1)* %gep2
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%gep3 = getelementptr float, float addrspace(1)* %out, i64 3
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store float %elt4, float addrspace(1)* %gep3
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ret void
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}
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; GCN-LABEL: {{^}}max_12regs_13a_used:
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; A2V-NOT: SCRATCH_RSRC
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; GFX908-DAG: v_accvgpr_read_b32 v[[VSPILL:[0-9]+]], a4
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; A2M: buffer_store_dword v[[VSPILL]], off, s[{{[0-9:]+}}], 0 offset:[[FI:[0-9]+]] ; 4-byte Folded Spill
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; A2M: buffer_load_dword v[[VSPILL:[0-9]+]], off, s[{{[0-9:]+}}], 0 offset:[[FI]] ; 4-byte Folded Reload
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; A2V: v_accvgpr_write_b32 a{{[0-9]+}}, v[[VSPILL]]
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; A2V: ScratchSize: 0
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define amdgpu_kernel void @max_12regs_13a_used(<4 x float> addrspace(1)* %arg, <4 x float> addrspace(1)* %out) #2 {
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bb:
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%in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
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%mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
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%mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 1.0, <4 x float> %mai.1, i32 0, i32 0, i32 0)
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br label %use
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use:
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call void asm sideeffect "", "a,a,a,a,a"(i32 1, i32 2, i32 3, i32 4, i32 5)
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store <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> addrspace(1)* %out
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br label %st
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st:
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%gep1 = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i64 16
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%gep2 = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i64 32
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store <4 x float> %mai.1, <4 x float> addrspace(1)* %gep1
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store <4 x float> %mai.2, <4 x float> addrspace(1)* %gep2
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ret void
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}
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; GCN-LABEL: {{^}}max_10_vgprs_used_9a:
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; A2V-NOT: SCRATCH_RSRC
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; GFX908-DAG: v_accvgpr_read_b32 v[[VSPILL:[0-9]+]], a0
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; A2M: buffer_store_dword v[[VSPILL]], off, s[{{[0-9:]+}}], 0 offset:[[FI:[0-9]+]] ; 4-byte Folded Spill
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; A2M: buffer_load_dword v[[VSPILL:[0-9]+]], off, s[{{[0-9:]+}}], 0 offset:[[FI]] ; 4-byte Folded Reload
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; GFX908: v_accvgpr_write_b32 a{{[0-9]+}}, v[[VSPILL]]
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; A2V: ScratchSize: 0
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define amdgpu_kernel void @max_10_vgprs_used_9a(i32 addrspace(1)* %p) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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call void asm sideeffect "", "a,a,a,a"(i32 1, i32 2, i32 3, i32 4)
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call void asm sideeffect "", "a,a,a,a,a"(i32 5, i32 6, i32 7, i32 8, i32 9)
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ret void
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}
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; GCN-LABEL: {{^}}max_32regs_mfma32:
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
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; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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; A2V-NOT: SCRATCH_RSRC
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; GFX908-DAG: v_accvgpr_read_b32 v[[VSPILL:[0-9]+]], a0
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; A2M: buffer_store_dword v[[VSPILL]], off, s[{{[0-9:]+}}], 0 offset:[[FI:[0-9]+]] ; 4-byte Folded Spill
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; A2M: buffer_load_dword v[[VSPILL:[0-9]+]], off, s[{{[0-9:]+}}], 0 offset:[[FI]] ; 4-byte Folded Reload
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; GFX908: v_accvgpr_write_b32 a{{[0-9]+}}, v[[VSPILL]]
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; A2V: ScratchSize: 0
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define amdgpu_kernel void @max_32regs_mfma32(float addrspace(1)* %arg) #3 {
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bb:
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%v = call i32 asm sideeffect "", "=a"()
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br label %use
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use:
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%mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 1.0, <32 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0, float 17.0, float 18.0, float 19.0, float 20.0, float 21.0, float 22.0, float 23.0, float 24.0, float 25.0, float 26.0, float 27.0, float 28.0, float 29.0, float 30.0, float 31.0, float 2.0>, i32 0, i32 0, i32 0)
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call void asm sideeffect "", "a"(i32 %v)
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%elt1 = extractelement <32 x float> %mai.1, i32 0
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store float %elt1, float addrspace(1)* %arg
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float, float, <16 x float>, i32, i32, i32)
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declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32)
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declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32, i32, i32)
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attributes #0 = { nounwind "amdgpu-num-vgpr"="24" }
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attributes #1 = { nounwind "amdgpu-num-vgpr"="8" }
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attributes #2 = { nounwind "amdgpu-num-vgpr"="12" }
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attributes #3 = { nounwind "amdgpu-num-vgpr"="32" }
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