73cea83a6f
When optimising for code size at the expense of performance, it is often worth saving and restoring some of r0-r3, if IPRA will be able to take advantage of them. This doesn't cost any extra code size if we already have a PUSH/POP pair, and increases the number of available registers across any calls to the function. We already have an optimisation which tries fold the subtract/add of the SP into the PUSH/POP by using extra registers, which somewhat conflicts with this. I've made the new optimisation less aggressive in cases where the existing one is likely to trigger, which gives better results than either of these optimisations by themselves. Differential revision: https://reviews.llvm.org/D69936
407 lines
15 KiB
LLVM
407 lines
15 KiB
LLVM
; RUN: llc -mtriple armv7a--none-eabi -enable-ipra=true -arm-extra-spills -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
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; RUN: llc -mtriple thumbv7a--none-eabi -enable-ipra=true -arm-extra-spills -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB2
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; RUN: llc -mtriple thumbv6m--none-eabi -enable-ipra=true -arm-extra-spills -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB1
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; This clobbers r0, and already needs a push/pop, so we also save and restore
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; r0. The push of r11 is to maintain stack alignment (though that isn't
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; technically needed in this example).
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define void @test_r0_r4() minsize nounwind {
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; CHECK-LABEL: test_r0_r4:
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; ARM: .save {r0, r4, r11, lr}
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; ARM: push {r0, r4, r11, lr}
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; ARM: pop {r0, r4, r11, pc}
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; THUMB1: .save {r0, r4, r7, lr}
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; THUMB1: push {r0, r4, r7, lr}
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; THUMB1: pop {r0, r4, r7, pc}
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; THUMB2: .save {r0, r4, r7, lr}
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; THUMB2: push {r0, r4, r7, lr}
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; THUMB2: pop {r0, r4, r7, pc}
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call void asm sideeffect "", "~{r0},~{r4}"()
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ret void
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}
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; This clobbers r0-r3, and already needs a push/pop, so we also save and
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; restore all of them.
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define void @test_r0_r1_r2_r3_r4() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4:
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; CHECK: .save {r0, r1, r2, r3, r4, lr}
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; CHECK: push {r0, r1, r2, r3, r4, lr}
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; CHECK: pop {r0, r1, r2, r3, r4, pc}
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
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ret void
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}
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; Check that IPRA does make use of the extra saved registers.
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define void @test_ipra() nounwind {
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; CHECK-LABEL: test_ipra:
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; CHECK: ASM1: r0, r1, r2, r3
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; CHECK-NOT: r0
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; CHECK-NOT: r1
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; CHECK-NOT: r2
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; CHECK-NOT: r3
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; CHECK: bl test_r0_r1_r2_r3_r4
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; CHECK-NOT: r0
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; CHECK-NOT: r1
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; CHECK-NOT: r2
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; CHECK-NOT: r3
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; CHECK: ASM2: r0, r1, r2, r3
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%regs = call { i32, i32, i32, i32 } asm sideeffect "// ASM1: $0, $1, $2, $3", "={r0},={r1},={r2},={r3}"()
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%r0 = extractvalue { i32, i32, i32, i32 } %regs, 0
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%r1 = extractvalue { i32, i32, i32, i32 } %regs, 1
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%r2 = extractvalue { i32, i32, i32, i32 } %regs, 2
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%r3 = extractvalue { i32, i32, i32, i32 } %regs, 3
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call void @test_r0_r1_r2_r3_r4()
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call void asm sideeffect "// ASM2: $0, $1, $2, $3", "{r0},{r1},{r2},{r3}"(i32 %r0, i32 %r1, i32 %r2, i32 %r3)
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ret void
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}
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; This clobbers r0-r3, but doesn't otherwise need a push/pop, so we don't add
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; them.
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define void @test_r0_r1_r2_r3() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3:
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; CHECK-NOT: push
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; CHECK-NOT: pop
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3}"()
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ret void
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}
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; This isn't called in this function, so we don't push any extra registers.
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define void @test_r0_r4_not_called() minsize nounwind {
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; CHECK-LABEL: test_r0_r4_not_called:
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; CHECK: .save {r4, lr}
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; CHECK: push {r4, lr}
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; CHECK: pop {r4, pc}
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; CHECK-NOT: push
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; CHECK-NOT: pop
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call void asm sideeffect "", "~{r0},~{r4}"()
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ret void
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}
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; This function is only optsize, not minsize, so we don't add any extra saves.
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define void @test_r0_r4_not_minsize() optsize nounwind {
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; CHECK-LABEL: test_r0_r4_not_minsize:
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; CHECK: .save {r4, lr}
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; CHECK: push {r4, lr}
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; CHECK: pop {r4, pc}
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; CHECK-NOT: push
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; CHECK-NOT: pop
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call void asm sideeffect "", "~{r0},~{r4}"()
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ret void
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}
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; This function is not an exact definition (the linker could pick an
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; alternative version of it), so we don't add any extra saves.
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define linkonce_odr void @test_r0_r4_not_exact() minsize nounwind {
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; CHECK-LABEL: test_r0_r4_not_exact:
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; CHECK: .save {r4, lr}
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; CHECK: push {r4, lr}
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; CHECK: pop {r4, pc}
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; CHECK-NOT: push
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; CHECK-NOT: pop
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call void asm sideeffect "", "~{r0},~{r4}"()
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ret void
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}
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; This clobbers r0-r3, but returns a value in r0, so only r1-r3 are saved.
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define i32 @test_r0_r1_r2_r3_r4_return_1() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_1:
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; ARM: .save {r1, r2, r3, r4, r11, lr}
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; ARM: push {r1, r2, r3, r4, r11, lr}
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; ARM: pop {r1, r2, r3, r4, r11, pc}
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; THUMB1: .save {r1, r2, r3, r4, r7, lr}
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; THUMB1: push {r1, r2, r3, r4, r7, lr}
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; THUMB1: pop {r1, r2, r3, r4, r7, pc}
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; THUMB2: .save {r1, r2, r3, r4, r7, lr}
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; THUMB2: push {r1, r2, r3, r4, r7, lr}
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; THUMB2: pop {r1, r2, r3, r4, r7, pc}
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
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ret i32 42
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}
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; This clobbers r0-r3, but returns a value in r0 and r1, so only r2-r3 are
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; saved.
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define i64 @test_r0_r1_r2_r3_r4_return_2() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_2:
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; CHECK: .save {r2, r3, r4, lr}
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; CHECK: push {r2, r3, r4, lr}
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; CHECK: pop {r2, r3, r4, pc}
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
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ret i64 42
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}
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; This clobbers r0-r3, but returns a value in all of r0-r3, so none of them can
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; be saved.
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define i128 @test_r0_r1_r2_r3_r4_return_4() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_4:
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; CHECK: .save {r4, lr}
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; CHECK: push {r4, lr}
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; CHECK: pop {r4, pc}
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
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ret i128 42
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}
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; This clobbers r0-r3, and returns a value in s0, so all of r0-r3 are saved (we
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; previously only checked the number of return registers, ignoring their
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; class).
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define arm_aapcs_vfpcc float @test_r0_r1_r2_r3_r4_return_float() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_return_float:
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; ARM: .save {r0, r1, r2, r3, r4, lr}
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; ARM: push {r0, r1, r2, r3, r4, lr}
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; ARM: pop {r0, r1, r2, r3, r4, pc}
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; THUMB1: .save {r1, r2, r3, r4, r7, lr}
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; THUMB1: push {r1, r2, r3, r4, r7, lr}
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; THUMB1: pop {r1, r2, r3, r4, r7, pc}
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; THUMB2: .save {r0, r1, r2, r3, r4, lr}
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; THUMB2: push {r0, r1, r2, r3, r4, lr}
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; THUMB2: pop {r0, r1, r2, r3, r4, pc}
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4}"()
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ret float 42.0
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}
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; Saving of high registers in thumb1 is more complicated, because they need to
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; be copied down to low registers to use push/pop instructions. Luckily, the
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; extra registers we are preserving are low registers, which are handled by the
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; outer-most push/pop pair, so this doesn't interact badly.
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define void @test_save_high_regs() minsize nounwind {
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; CHECK-LABEL: test_save_high_regs:
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; ARM: .save {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
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; ARM: push {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
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; ARM: pop {r0, r1, r2, r3, r7, r8, r9, r10, r11, pc}
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; THUMB1: .save {r0, r1, r2, r3, r7, lr}
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; THUMB1-NEXT: push {r0, r1, r2, r3, r7, lr}
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; THUMB1-NEXT: mov lr, r11
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; THUMB1-NEXT: mov r7, r10
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; THUMB1-NEXT: mov r3, r9
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; THUMB1-NEXT: mov r2, r8
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; THUMB1-NEXT: .save {r8, r9, r10, r11}
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; THUMB1-NEXT: push {r2, r3, r7, lr}
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; THUMB1: pop {r0, r1, r2, r3}
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; THUMB1-NEXT: mov r8, r0
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; THUMB1-NEXT: mov r9, r1
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; THUMB1-NEXT: mov r10, r2
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; THUMB1-NEXT: mov r11, r3
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; THUMB1-NEXT: pop {r0, r1, r2, r3, r7, pc}
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; THUMB2: .save {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
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; THUMB2: push.w {r0, r1, r2, r3, r7, r8, r9, r10, r11, lr}
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; THUMB2: pop.w {r0, r1, r2, r3, r7, r8, r9, r10, r11, pc}
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r8},~{r9},~{r10},~{r11}"()
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ret void
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}
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; We can also use extra registers in the PUSH/POP instructions to move the SP
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; to make space for local variables. These registers aren't preserved, because
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; the space they are saved in is used for the local variable. We try to back
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; off the extra-CSRs optimisation to allow this to still happen. In this case,
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; there are 8 bytes of stack space needed, so we preserve two argument
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; registers and use the other two for the SP update.
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define void @test_r0_r1_r2_r3_r4_stack8() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack8:
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; CHECK: .save {r2, r3, r4, lr}
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; CHECK: push {r0, r1, r2, r3, r4, lr}
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; CHECK: pop {r0, r1, r2, r3, r4, pc}
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%a = alloca [2 x i32], align 4
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call void asm sideeffect "str $1, [$0]; str $1, [$0, #4]", "{r0},{r1},~{r2},~{r3},~{r4}"([2 x i32]* %a, i32 42)
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ret void
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}
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; Check that, when the above function is called, r0 and r1 (used for the SP
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; updates) are considered clobbered, and r2 and r3 are preserved.
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define void @test_r0_r1_r2_r3_r4_stack8_caller() nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack8_caller:
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; CHECK: ASM1: r0, r1, r2, r3
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: mov r4, r0
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; CHECK-NEXT: mov r5, r1
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; CHECK-NEXT: bl test_r0_r1_r2_r3_r4
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: @APP
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; CHECK-NEXT: ASM2: r0, r1, r2, r3
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%regs = call { i32, i32, i32, i32 } asm sideeffect "// ASM1: $0, $1, $2, $3", "={r0},={r1},={r2},={r3}"()
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%r0 = extractvalue { i32, i32, i32, i32 } %regs, 0
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%r1 = extractvalue { i32, i32, i32, i32 } %regs, 1
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%r2 = extractvalue { i32, i32, i32, i32 } %regs, 2
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%r3 = extractvalue { i32, i32, i32, i32 } %regs, 3
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call void @test_r0_r1_r2_r3_r4_stack8()
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call void asm sideeffect "// ASM2: $0, $1, $2, $3", "{r0},{r1},{r2},{r3}"(i32 %r0, i32 %r1, i32 %r2, i32 %r3)
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ret void
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}
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; Like @test_r0_r1_r2_r3_r4_stack8, but 16 bytes of stack space are needed, so
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; all of r0-r3 are used for the SP update, and not preserved.
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define void @test_r0_r1_r2_r3_r4_stack16() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack16:
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; CHECK: .save {r4, lr}
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; CHECK: push {r0, r1, r2, r3, r4, lr}
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; CHECK: pop {r0, r1, r2, r3, r4, pc}
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%a = alloca [4 x i32], align 4
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call void asm sideeffect "str $1, [$0]; str $1, [$0, #4]", "{r0},{r1},~{r2},~{r3},~{r4}"([4 x i32]* %a, i32 42)
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ret void
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}
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; If more than 16 bytes of stack space are needed, it's unlikely that the
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; SP-update folding optimisation will succeed, so we revert back to preserving
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; r0-r3 for use in our callers.
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define void @test_r0_r1_r2_r3_r4_stack24() minsize nounwind {
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; CHECK-LABEL: test_r0_r1_r2_r3_r4_stack24:
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; CHECK: .save {r0, r1, r2, r3, r4, lr}
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; CHECK: push {r0, r1, r2, r3, r4, lr}
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; CHECK: pop {r0, r1, r2, r3, r4, pc}
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%a = alloca [6 x i32], align 4
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call void asm sideeffect "str $1, [$0]; str $1, [$0, #4]", "{r0},{r1},~{r2},~{r3},~{r4}"([6 x i32]* %a, i32 42)
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ret void
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}
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define i32 @tail_callee(i32 %a, i32 %b) minsize nounwind {
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entry:
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tail call void asm sideeffect "", "~{r2}"()
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ret i32 %a
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}
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; The tail call happens outside the save/restore region, so prevents us from
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; preserving some registers. r0 and r1 are outgoing arguments to the tail-call,
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; so can't be preserved. r2 is modified inside the tail-called function, so
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; can't be presrved. r3 is known to be preserved by the callee, so can be
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; presrved. For Thumb1, we can't (efficiently) use a tail-call here, so r1-r3
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; are all preserved, with r0 being the return value.
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define i32 @test_tail_call() minsize nounwind {
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entry:
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; CHECK-LABEL: test_tail_call:
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; ARM: .save {r3, lr}
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; ARM: push {r3, lr}
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; ARM: pop {r3, lr}
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; ARM: b tail_callee
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; THUMB2: .save {r3, lr}
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; THUMB2: push {r3, lr}
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; THUMB2: pop.w {r3, lr}
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; THUMB2: b tail_callee
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; THUMB1: .save {r1, r2, r3, lr}
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; THUMB1: push {r1, r2, r3, lr}
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; THUMB1: bl tail_callee
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; THUMB1: pop {r1, r2, r3, pc}
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tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{lr}"()
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%call = tail call i32 @tail_callee(i32 3, i32 4)
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ret i32 %call
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}
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declare i32 @tail_callee_external(i32 %a, i32 %b)
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; If we tail-call an external function, it could clobber any of r0-r3.
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define i32 @test_tail_call_external() minsize nounwind {
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entry:
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; CHECK-LABEL: test_tail_call_external:
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; ARM: .save {r11, lr}
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; ARM: push {r11, lr}
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; ARM: pop {r11, lr}
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; ARM: b tail_callee_external
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; THUMB2: .save {r7, lr}
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; THUMB2: push {r7, lr}
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; THUMB2: pop.w {r7, lr}
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; THUMB2: b tail_callee_external
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; THUMB1: .save {r1, r2, r3, lr}
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; THUMB1: push {r1, r2, r3, lr}
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; THUMB1: bl tail_callee_external
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; THUMB1: pop {r1, r2, r3, pc}
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tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{lr}"()
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%call = tail call i32 @tail_callee_external(i32 3, i32 4)
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ret i32 %call
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}
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define linkonce_odr i32 @tail_callee_linkonce_odr(i32 %a, i32 %b) minsize nounwind {
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entry:
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tail call void asm sideeffect "", "~{r2}"()
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ret i32 %a
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}
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; If a tail-callee has an interposable linkage type (such as linkonce_odr), we
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; can't assume the linker will pick the definition we can see, so must assume
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; it clobbers all of r0-r3.
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define i32 @test_tail_call_linkonce_odr() minsize nounwind {
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entry:
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; CHECK-LABEL: test_tail_call_linkonce_odr:
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; ARM: .save {r11, lr}
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; ARM: push {r11, lr}
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; ARM: pop {r11, lr}
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; ARM: b tail_callee_linkonce_odr
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; THUMB2: .save {r7, lr}
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; THUMB2: push {r7, lr}
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; THUMB2: pop.w {r7, lr}
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|
; THUMB2: b tail_callee_linkonce_odr
|
|
; THUMB1: .save {r1, r2, r3, lr}
|
|
; THUMB1: push {r1, r2, r3, lr}
|
|
; THUMB1: bl tail_callee_linkonce_odr
|
|
; THUMB1: pop {r1, r2, r3, pc}
|
|
tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{lr}"()
|
|
%call = tail call i32 @tail_callee_linkonce_odr(i32 3, i32 4)
|
|
ret i32 %call
|
|
}
|
|
|
|
; This function doesn't have the nounwind attribute, so unwind tables will be
|
|
; emitted. Saving r0-r3 requires a longer unwind instruction sequence, which
|
|
; results in an increase in total code size if there are few callers to make
|
|
; use of the extra registers.
|
|
define void @test_unwind_tables() minsize {
|
|
; CHECK-LABEL: test_unwind_tables:
|
|
; ARM: .save {r4, lr}
|
|
; ARM: push {r4, lr}
|
|
; ARM: pop {r4, pc}
|
|
; THUMB1: .save {r4, lr}
|
|
; THUMB1: push {r4, lr}
|
|
; THUMB1: pop {r4, pc}
|
|
; THUMB2: .save {r4, lr}
|
|
; THUMB2: push {r4, lr}
|
|
; THUMB2: pop {r4, pc}
|
|
call void asm sideeffect "", "~{r0},~{r4}"()
|
|
ret void
|
|
}
|
|
|
|
; This requires an unwind table, but has many call sites, so overall we expect
|
|
; the benefits to outweigh the size increase of the unwind table.
|
|
define void @test_unwind_tables_many_calls() minsize {
|
|
; CHECK-LABEL: test_unwind_tables_many_calls:
|
|
; ARM: .save {r0, r4, r11, lr}
|
|
; ARM: push {r0, r4, r11, lr}
|
|
; ARM: pop {r0, r4, r11, pc}
|
|
; THUMB1: .save {r0, r4, r7, lr}
|
|
; THUMB1: push {r0, r4, r7, lr}
|
|
; THUMB1: pop {r0, r4, r7, pc}
|
|
; THUMB2: .save {r0, r4, r7, lr}
|
|
; THUMB2: push {r0, r4, r7, lr}
|
|
; THUMB2: pop {r0, r4, r7, pc}
|
|
call void asm sideeffect "", "~{r0},~{r4}"()
|
|
ret void
|
|
}
|
|
|
|
; We don't do this optimisation is there are no callers in the same translation
|
|
; unit (otherwise IPRA wouldn't be able to take advantage of the extra saved
|
|
; registers), so most functions in this file are called here.
|
|
define void @caller() {
|
|
; CHECK-LABEL: caller:
|
|
call void @test_r0_r4()
|
|
call void @test_r0_r1_r2_r3_r4()
|
|
call void @test_r0_r1_r2_r3()
|
|
call void @test_r0_r4_not_minsize()
|
|
call void @test_r0_r4_not_exact()
|
|
%t1 = call i32 @test_r0_r1_r2_r3_r4_return_1()
|
|
%t2 = call i64 @test_r0_r1_r2_r3_r4_return_2()
|
|
%t3 = call i128 @test_r0_r1_r2_r3_r4_return_4()
|
|
%t4 = call float @test_r0_r1_r2_r3_r4_return_float()
|
|
call void @test_save_high_regs()
|
|
call void @test_r0_r1_r2_r3_r4_stack16()
|
|
call void @test_r0_r1_r2_r3_r4_stack24()
|
|
%t5 = call i32 @test_tail_call()
|
|
%t6 = call i32 @test_tail_call_external()
|
|
%t7 = call i32 @test_tail_call_linkonce_odr()
|
|
call void @test_unwind_tables()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
call void @test_unwind_tables_many_calls()
|
|
ret void
|
|
}
|