019ab61e25
This allow it to recognize more loads as being consecutive when the load's address are complex at the start. Differential Revision: https://reviews.llvm.org/D74444
102 lines
3.2 KiB
LLVM
102 lines
3.2 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; Even though general vector types are not supported in PTX, we can still
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; optimize loads/stores with pseudo-vector instructions of the form:
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;
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; ld.v2.f32 {%f0, %f1}, [%r0]
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;
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; which will load two floats at once into scalar registers.
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; CHECK-LABEL foo
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define void @foo(<2 x float>* %a) {
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; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = load <2 x float>, <2 x float>* %a
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%t2 = fmul <2 x float> %t1, %t1
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store <2 x float> %t2, <2 x float>* %a
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ret void
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}
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; CHECK-LABEL foo2
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define void @foo2(<4 x float>* %a) {
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; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = load <4 x float>, <4 x float>* %a
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%t2 = fmul <4 x float> %t1, %t1
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store <4 x float> %t2, <4 x float>* %a
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ret void
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}
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; CHECK-LABEL foo3
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define void @foo3(<8 x float>* %a) {
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; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = load <8 x float>, <8 x float>* %a
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%t2 = fmul <8 x float> %t1, %t1
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store <8 x float> %t2, <8 x float>* %a
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ret void
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}
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; CHECK-LABEL foo4
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define void @foo4(<2 x i32>* %a) {
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; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}}
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%t1 = load <2 x i32>, <2 x i32>* %a
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%t2 = mul <2 x i32> %t1, %t1
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store <2 x i32> %t2, <2 x i32>* %a
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ret void
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}
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; CHECK-LABEL foo5
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define void @foo5(<4 x i32>* %a) {
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; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
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%t1 = load <4 x i32>, <4 x i32>* %a
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%t2 = mul <4 x i32> %t1, %t1
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store <4 x i32> %t2, <4 x i32>* %a
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ret void
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}
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; CHECK-LABEL foo6
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define void @foo6(<8 x i32>* %a) {
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; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
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; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
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%t1 = load <8 x i32>, <8 x i32>* %a
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%t2 = mul <8 x i32> %t1, %t1
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store <8 x i32> %t2, <8 x i32>* %a
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ret void
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}
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; The following test wasn't passing previously as the address
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; computation was still too complex when LSV was called.
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declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #0
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #0
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; CHECK-LABEL foo_complex
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define void @foo_complex(i8* nocapture readonly align 16 dereferenceable(134217728) %alloc0) {
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%targ0.1.typed = bitcast i8* %alloc0 to [1024 x [131072 x i8]]*
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%t0 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !1
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%t1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
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%t2 = lshr i32 %t1, 8
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%t3 = shl nuw nsw i32 %t1, 9
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%ttile_origin.2 = and i32 %t3, 130560
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%tstart_offset_x_mul = shl nuw nsw i32 %t0, 1
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%t4 = or i32 %ttile_origin.2, %tstart_offset_x_mul
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%t6 = or i32 %t4, 1
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%t8 = or i32 %t4, 128
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%t9 = zext i32 %t8 to i64
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%t10 = or i32 %t4, 129
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%t11 = zext i32 %t10 to i64
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%t20 = zext i32 %t2 to i64
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%t27 = getelementptr inbounds [1024 x [131072 x i8]], [1024 x [131072 x i8]]* %targ0.1.typed, i64 0, i64 %t20, i64 %t9
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; CHECK: ld.v2.u8
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%t28 = load i8, i8* %t27, align 2
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%t31 = getelementptr inbounds [1024 x [131072 x i8]], [1024 x [131072 x i8]]* %targ0.1.typed, i64 0, i64 %t20, i64 %t11
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%t32 = load i8, i8* %t31, align 1
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%t33 = icmp ult i8 %t28, %t32
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%t34 = select i1 %t33, i8 %t32, i8 %t28
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store i8 %t34, i8* %t31
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; CHECK: ret
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ret void
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}
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!1 = !{i32 0, i32 64}
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