2f0c7fd2db
The initial attempt (rG89633320) botched the logic by reversing the source/dest types. Added x86 tests for additional coverage. The vector tests show a potential improvement (fold vector load instead of broadcasting), but that's a known/existing problem. This fold is done in IR by instcombine, and we have a special form of it already here in DAGCombiner, but we want the more general transform too: https://rise4fun.com/Alive/3jZm Name: general Pre: (C1 + zext(C2) < 64) %s = lshr i64 %x, C1 %t = trunc i64 %s to i16 %r = lshr i16 %t, C2 => %s2 = lshr i64 %x, C1 + zext(C2) %a = and i64 %s2, zext((1 << (16 - C2)) - 1) %r = trunc %a to i16 Name: special Pre: C1 == 48 %s = lshr i64 %x, C1 %t = trunc i64 %s to i16 %r = lshr i16 %t, C2 => %s2 = lshr i64 %x, C1 + zext(C2) %r = trunc %s2 to i16 ...because D58017 exposes a regression without this fold.
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
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define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
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; CHECK-LABEL: trunc_srl_load:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lhz 4, 2(0)
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; CHECK-NEXT: cmplw 0, 4, 3
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; CHECK-NEXT: ble 0, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %exit
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; CHECK-NEXT: .LBB0_2: # %cond.false
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entry:
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%bf.load.i = load i64, i64* null, align 8
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%bf.lshr.i = lshr i64 %bf.load.i, 32
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%0 = trunc i64 %bf.lshr.i to i32
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%bf.cast.i = and i32 %0, 65535
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%cmp.i = icmp ugt i32 %bf.cast.i, %AttrArgNo
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br i1 %cmp.i, label %exit, label %cond.false
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exit: ; preds = %entry
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unreachable
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cond.false: ; preds = %entry
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unreachable
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}
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define i32 @sh_trunc_sh(i64 %x) {
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; CHECK-LABEL: sh_trunc_sh:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldicl 3, 3, 47, 36
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; CHECK-NEXT: blr
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%s = lshr i64 %x, 13
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%t = trunc i64 %s to i32
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%r = lshr i32 %t, 4
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ret i32 %r
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}
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