7efabe5c7d
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
298 lines
17 KiB
YAML
298 lines
17 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
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--- |
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define dso_local arm_aapcs_vfpcc void @skip_debug(i32* nocapture %a, i16* nocapture readonly %b, i32 %N) !dbg !8 {
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entry:
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call void @llvm.dbg.value(metadata i32* %a, metadata !17, metadata !DIExpression()), !dbg !23
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call void @llvm.dbg.value(metadata i16* %b, metadata !18, metadata !DIExpression()), !dbg !23
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call void @llvm.dbg.value(metadata i32 %N, metadata !19, metadata !DIExpression()), !dbg !23
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%0 = load i32, i32* %a, align 4, !dbg !24
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call void @llvm.dbg.value(metadata i32 %0, metadata !20, metadata !DIExpression()), !dbg !23
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call void @llvm.dbg.value(metadata i32 0, metadata !21, metadata !DIExpression()), !dbg !29
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%cmp7 = icmp eq i32 %N, 0, !dbg !30
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%1 = add i32 %N, 3, !dbg !32
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%2 = lshr i32 %1, 2, !dbg !32
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%3 = shl nuw i32 %2, 2, !dbg !32
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%4 = add i32 %3, -4, !dbg !32
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%5 = lshr i32 %4, 2, !dbg !32
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%6 = add nuw nsw i32 %5, 1, !dbg !32
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br i1 %cmp7, label %for.cond.cleanup, label %vector.ph, !dbg !32
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vector.ph: ; preds = %entry
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%7 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %0, i32 0, !dbg !32
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call void @llvm.set.loop.iterations.i32(i32 %6), !dbg !32
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%8 = shl i32 %5, 2, !dbg !32
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%9 = sub i32 %N, %8, !dbg !32
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br label %vector.body, !dbg !32
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %b, %vector.ph ], !dbg !33
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%vec.phi = phi <4 x i32> [ %7, %vector.ph ], [ %15, %vector.body ]
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%10 = phi i32 [ %6, %vector.ph ], [ %16, %vector.body ]
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%11 = phi i32 [ %N, %vector.ph ], [ %13, %vector.body ]
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%lsr.iv14 = bitcast i16* %lsr.iv to <4 x i16>*
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%12 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %11), !dbg !34
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%13 = sub i32 %11, 4, !dbg !34
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%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv14, i32 2, <4 x i1> %12, <4 x i16> undef), !dbg !34
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%14 = sext <4 x i16> %wide.masked.load to <4 x i32>, !dbg !34
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%15 = sub <4 x i32> %vec.phi, %14, !dbg !38
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%scevgep = getelementptr i16, i16* %lsr.iv, i32 4, !dbg !33
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%16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %10, i32 1), !dbg !33
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%17 = icmp ne i32 %16, 0, !dbg !33
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br i1 %17, label %vector.body, label %middle.block, !dbg !33
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middle.block: ; preds = %vector.body
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%vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ]
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%.lcssa = phi <4 x i32> [ %15, %vector.body ], !dbg !38
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%18 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %9), !dbg !34
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%19 = select <4 x i1> %18, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa, !dbg !38
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%20 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %19), !dbg !32
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br label %for.cond.cleanup, !dbg !42
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for.cond.cleanup: ; preds = %middle.block, %entry
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%temp.0.lcssa = phi i32 [ %0, %entry ], [ %20, %middle.block ], !dbg !23
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call void @llvm.dbg.value(metadata i32 %temp.0.lcssa, metadata !20, metadata !DIExpression()), !dbg !23
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store i32 %temp.0.lcssa, i32* %a, align 4, !dbg !42
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ret void, !dbg !43
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}
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
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declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
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declare void @llvm.set.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4, !5, !6}
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!llvm.ident = !{!7}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
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!1 = !DIFile(filename: "skip-debug", directory: "")
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!2 = !{}
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!3 = !{i32 7, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = !{i32 1, !"wchar_size", i32 4}
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!6 = !{i32 1, !"min_enum_size", i32 4}
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!7 = !{!""}
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!8 = distinct !DISubprogram(name: "skip_debug", scope: !1, file: !1, line: 2, type: !9, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16)
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!9 = !DISubroutineType(types: !10)
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!10 = !{null, !11, !13, !15}
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!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 32)
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!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
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!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 32)
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!14 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)
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!15 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
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!16 = !{!17, !18, !19, !20, !21}
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!17 = !DILocalVariable(name: "a", arg: 1, scope: !8, file: !1, line: 2, type: !11)
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!18 = !DILocalVariable(name: "b", arg: 2, scope: !8, file: !1, line: 2, type: !13)
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!19 = !DILocalVariable(name: "N", arg: 3, scope: !8, file: !1, line: 2, type: !15)
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!20 = !DILocalVariable(name: "temp", scope: !8, file: !1, line: 3, type: !12)
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!21 = !DILocalVariable(name: "i", scope: !22, file: !1, line: 4, type: !15)
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!22 = distinct !DILexicalBlock(scope: !8, file: !1, line: 4, column: 3)
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!23 = !DILocation(line: 0, scope: !8)
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!24 = !DILocation(line: 3, column: 14, scope: !8)
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!25 = !{!26, !26, i64 0}
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!26 = !{!"int", !27, i64 0}
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!27 = !{!"omnipotent char", !28, i64 0}
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!28 = !{!"Simple C/C++ TBAA"}
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!29 = !DILocation(line: 0, scope: !22)
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!30 = !DILocation(line: 4, column: 26, scope: !31)
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!31 = distinct !DILexicalBlock(scope: !22, file: !1, line: 4, column: 3)
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!32 = !DILocation(line: 4, column: 3, scope: !22)
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!33 = !DILocation(line: 4, column: 31, scope: !31)
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!34 = !DILocation(line: 5, column: 13, scope: !35)
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!35 = distinct !DILexicalBlock(scope: !31, file: !1, line: 4, column: 36)
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!36 = !{!37, !37, i64 0}
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!37 = !{!"short", !27, i64 0}
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!38 = !DILocation(line: 5, column: 10, scope: !35)
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!39 = distinct !{!39, !32, !40, !41}
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!40 = !DILocation(line: 6, column: 3, scope: !22)
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!41 = !{!"llvm.loop.isvectorized", i32 1}
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!42 = !DILocation(line: 7, column: 6, scope: !8)
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!43 = !DILocation(line: 8, column: 1, scope: !8)
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...
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---
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name: skip_debug
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 16
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offsetAdjustment: -8
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: skip_debug
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r6
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; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
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; CHECK: DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
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; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
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; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
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; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
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; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
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; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
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; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !24 :: (load 4 from %ir.a)
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; CHECK: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25
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; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
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; CHECK: tCBZ $r2, %bb.4, debug-location !28
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; CHECK: bb.1.vector.ph:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2, $r12
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; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28
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; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28
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; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28
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; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !28
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; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28
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; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28
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; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28
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; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28
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; CHECK: $lr = t2DLS killed renamable $lr, debug-location !28
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; CHECK: bb.2.vector.body:
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !30
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; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30
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; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1
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; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30
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; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !30 :: (load 8 from %ir.lsr.iv14, align 2)
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; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30
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; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !30
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; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !32
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29
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; CHECK: bb.3.middle.block:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: liveins: $q0, $q1, $r0, $r3
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; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !30
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; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !32
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; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !28
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; CHECK: bb.4.for.cond.cleanup:
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; CHECK: liveins: $r0, $r12
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; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
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; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store 4 into %ir.a)
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34
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bb.0.entry:
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successors: %bb.4(0x30000000), %bb.1(0x50000000)
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liveins: $r0, $r1, $r2, $r4, $r6, $lr
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DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
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DBG_VALUE $r0, $noreg, !17, !DIExpression(), debug-location !23
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DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
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DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23
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DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
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DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23
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frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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frame-setup CFI_INSTRUCTION offset $r6, -12
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frame-setup CFI_INSTRUCTION offset $r4, -16
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$r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa $r7, 8
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renamable $r12 = t2LDRi12 renamable $r0, 0, 14, $noreg, debug-location !24 :: (load 4 from %ir.a)
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DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !29
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DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
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tCBZ $r2, %bb.4, debug-location !32
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bb.1.vector.ph:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2, $r12
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renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !32
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renamable $lr = t2MOVi 1, 14, $noreg, $noreg
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renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !32
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !32
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renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !32
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renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !32
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renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !32
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renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !32
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renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !32
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t2DoLoopStart renamable $lr, debug-location !32
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bb.2.vector.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r2, $r3
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|
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renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !34
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DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !34
|
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$q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1
|
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MVE_VPST 8, implicit $vpr, debug-location !34
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|
renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !34 :: (load 8 from %ir.lsr.iv14, align 2)
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|
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !34
|
|
renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !34
|
|
renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !33
|
|
renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !38
|
|
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr, debug-location !33
|
|
tB %bb.3, 14, $noreg, debug-location !33
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|
|
|
bb.3.middle.block:
|
|
successors: %bb.4(0x80000000)
|
|
liveins: $q0, $q1, $r0, $r3
|
|
|
|
renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !34
|
|
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !38
|
|
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !32
|
|
|
|
bb.4.for.cond.cleanup:
|
|
liveins: $r0, $r12
|
|
|
|
DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
|
|
t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !42 :: (store 4 into %ir.a)
|
|
tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !43
|
|
|
|
...
|