Thomas Lively aff679a48c [WebAssembly] Implement remaining relaxed SIMD instructions ...

Add codegen, intrinsics, and builtins for the i16x8.relaxed_q15mulr_s,
i16x8.dot_i8x16_i7x16_s, and i32x4.dot_i8x16_i7x16_add_s instructions. These are
the last instructions from the relaxed SIMD proposal[1] that had not been
implemented.

[1]:
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md.

Differential Revision: https://reviews.llvm.org/D127170

2022-06-08 10:32:10 -07:00

..

AArch64

[AArch64] Remove ToBeRemoved from AArch64MIPeepholeOpt

2022-06-08 17:26:07 +01:00

AMDGPU

llvm-reduce: Don't assert on functions which don't track liveness

2022-06-07 10:00:25 -04:00

ARC

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ARM

[ARM] [MinGW] Default to WinEH exception handling instead of Dwarf

2022-06-06 23:27:19 +03:00

AVR

[FileCheck] Catch missspelled directives.

2022-05-26 11:37:19 +01:00

BPF

[BPF] Add BTF 64bit enum value support

2022-06-06 11:35:50 -07:00

CSKY

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DirectX

[DirectX][Fail crash in DXILPrepareModule pass when input has typed ptr.

2022-06-07 21:11:24 -07:00

Generic

[llvm][DWARF] Move test using X86 triple into X86 tests

2022-05-26 09:27:23 +00:00

Hexagon

[Hexagon] Regenerate build-vector-v4i8-zext.ll to show full codegen

2022-06-08 11:50:49 +01:00

Inputs

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Lanai

[Support] Make report_fatal_error respect its GenCrashDiag argument so it doesn't generate a backtrace

2022-05-30 19:19:23 +01:00

LoongArch

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M68k

[M68k] Instruction selection to choose neg x when mul x -1 (Fix issue 48588)

2022-06-03 13:20:30 +08:00

Mips

llvm-reduce: Don't assert on functions which don't track liveness

2022-06-07 10:00:25 -04:00

MIR

llvm-reduce: Don't assert on functions which don't track liveness

2022-06-07 10:00:25 -04:00

MLRegalloc

[mlgo] Fix test

2022-05-11 10:07:40 -07:00

MSP430

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NVPTX

[NVPTX] Enable AtomicExpandPass for NVPTX

2022-05-20 17:25:28 -04:00

PowerPC

[PowerPC] Support huge frame size for PPC64

2022-06-06 09:08:28 +00:00

RISCV

[RISCV] Support (addi (addi globaladdr, C1), C2) in RISCVMergeBaseOffset.

2022-06-08 08:20:37 -07:00

SPARC

[SPARC] Fix type for i64 inline asm operands

2022-06-04 18:32:16 -04:00

SPIRV

[SPIRV] Add simple tests to improve test coverage

2022-05-19 01:44:38 +03:00

SystemZ

[SystemZ] Use STDY/STEY/LDY/LEY for VR32/VR64 in eliminateFrameIndex().

2022-06-08 17:10:31 +02:00

Thumb

[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.

2022-06-02 00:49:11 +00:00

Thumb2

[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.

2022-06-02 00:49:11 +00:00

VE

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WebAssembly

[WebAssembly] Implement remaining relaxed SIMD instructions

2022-06-08 10:32:10 -07:00

WinCFGuard

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WinEH

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X86

[X86] Regenerate slow-pmulld.ll with common SSE check prefixes

2022-06-08 18:23:25 +01:00

XCore

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