Matt Arsenault b02cebf552 AMDGPU: Fix incorrect reordering when inline asm defines LDS address ...

Defs of operands outside of the instruction's explicit defs need
to be checked.

llvm-svn: 324554

2018-02-08 01:56:14 +00:00

..

AArch64

[LegalizeDAG] Truncate condition operand of ISD::SELECT

2018-02-07 05:38:29 +00:00

AMDGPU

AMDGPU: Fix incorrect reordering when inline asm defines LDS address

2018-02-08 01:56:14 +00:00

ARC

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ARM

[ARM] FP16 mov imm pattern

2018-02-07 08:37:17 +00:00

AVR

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BPF

[DWARF] Regularize dumping strings from line tables.

2018-02-05 20:43:15 +00:00

Generic

[MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default."

2018-02-07 09:58:55 +00:00

Hexagon

[Hexagon] Lower concat of more than 2 vectors into build_vector

2018-02-06 20:18:58 +00:00

Inputs

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Lanai

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

[mips] Support 'y' operand code to print exact log2 of the operand

2018-02-07 12:36:39 +00:00

MIR

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

MSP430

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Nios2

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NVPTX

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PowerPC

[MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default."

2018-02-07 09:58:55 +00:00

RISCV

[RISCV] Update two RISCV codegen tests after rL323991

2018-02-03 13:02:30 +00:00

SPARC

[MachineCopyPropagation] Extend pass to do COPY source forwarding

2018-02-01 18:54:01 +00:00

SystemZ

[SelectionDAG] Consider endianness in scalarizeVectorStore().

2018-02-02 08:48:02 +00:00

Thumb

[LivePhysRegs] Fix handling of return instructions.

2018-02-06 23:00:17 +00:00

Thumb2

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

WebAssembly

[WebAssembly] Fix test expectations after r324274

2018-02-06 01:21:17 +00:00

WinCFGuard

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WinEH

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X86

[x86] Fix nasty bug in the x86 backend that is essentially impossible to

2018-02-07 23:59:14 +00:00

XCore

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