058cd8c5be
Summary: This patch tries to ensure that we do something sensible when generating code for the ISD::INSERT_VECTOR_ELT DAG node when operating on scalable vectors. Previously we always returned 'undef' when inserting an element into an out-of-bounds lane index, whereas now we only do this for fixed length vectors. For scalable vectors it is assumed that the backend will do the right thing in the same way that we have to deal with variable lane indices. In this patch I have permitted a few basic combinations for scalable vector types where it makes sense, but in general avoided most cases for now as they currently require the use of BUILD_VECTOR nodes. This patch includes tests for all scalable vector types when inserting into lane 0, but I've only included one or two vector types for other cases such as variable lane inserts. Differential Revision: https://reviews.llvm.org/D78992
136 lines
5.0 KiB
LLVM
136 lines
5.0 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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define <vscale x 16 x i8> @test_lane0_16xi8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: test_lane0_16xi8
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; CHECK: mov [[REG:.*]], #30
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; CHECK: mov z0.b, p{{[0-7]}}/m, [[REG]]
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%b = insertelement <vscale x 16 x i8> %a, i8 30, i32 0
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ret <vscale x 16 x i8> %b
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}
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define <vscale x 8 x i16> @test_lane0_8xi16(<vscale x 8 x i16> %a) {
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; CHECK-LABEL: test_lane0_8xi16
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; CHECK: mov [[REG:.*]], #30
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; CHECK: mov z0.h, p{{[0-7]}}/m, [[REG]]
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%b = insertelement <vscale x 8 x i16> %a, i16 30, i32 0
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ret <vscale x 8 x i16> %b
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}
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define <vscale x 4 x i32> @test_lane0_4xi32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: test_lane0_4xi32
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; CHECK: mov [[REG:.*]], #30
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; CHECK: mov z0.s, p{{[0-7]}}/m, [[REG]]
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%b = insertelement <vscale x 4 x i32> %a, i32 30, i32 0
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ret <vscale x 4 x i32> %b
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}
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define <vscale x 2 x i64> @test_lane0_2xi64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: test_lane0_2xi64
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; CHECK: mov w[[REG:.*]], #30
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; CHECK: mov z0.d, p{{[0-7]}}/m, x[[REG]]
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%b = insertelement <vscale x 2 x i64> %a, i64 30, i32 0
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ret <vscale x 2 x i64> %b
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}
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define <vscale x 2 x double> @test_lane0_2xf64(<vscale x 2 x double> %a) {
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; CHECK-LABEL: test_lane0_2xf64
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; CHECK: fmov d[[REG:[0-9]+]], #1.00000000
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; CHECK: mov z0.d, p{{[0-7]}}/m, z[[REG]].d
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%b = insertelement <vscale x 2 x double> %a, double 1.0, i32 0
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ret <vscale x 2 x double> %b
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}
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define <vscale x 4 x float> @test_lane0_4xf32(<vscale x 4 x float> %a) {
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; CHECK-LABEL: test_lane0_4xf32
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; CHECK: fmov s[[REG:[0-9]+]], #1.00000000
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; CHECK: mov z0.s, p{{[0-7]}}/m, z[[REG]].s
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%b = insertelement <vscale x 4 x float> %a, float 1.0, i32 0
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ret <vscale x 4 x float> %b
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}
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define <vscale x 8 x half> @test_lane0_8xf16(<vscale x 8 x half> %a) {
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; CHECK-LABEL: test_lane0_8xf16
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; CHECK: fmov h[[REG:[0-9]+]], #1.00000000
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; CHECK: mov z0.h, p{{[0-7]}}/m, z[[REG]].h
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%b = insertelement <vscale x 8 x half> %a, half 1.0, i32 0
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ret <vscale x 8 x half> %b
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}
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; Undefined lane insert
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define <vscale x 2 x i64> @test_lane4_2xi64(<vscale x 2 x i64> %a) {
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; CHECK-LABEL: test_lane4_2xi64
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; CHECK: mov w[[IDXREG:.*]], #4
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; CHECK: index z[[CMPVEC:[0-9]+]].d, #0, #1
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; CHECK: mov z[[IDXVEC:[0-9]+]].d, x[[IDXREG]]
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; CHECK: cmpeq p[[PRED:[0-9]+]].d, p{{[0-7]}}/z, z[[CMPVEC]].d, z[[IDXVEC]].d
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; CHECK: mov w[[VALREG:.*]], #30
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; CHECK: mov z0.d, p[[PRED]]/m, x[[VALREG]]
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%b = insertelement <vscale x 2 x i64> %a, i64 30, i32 4
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ret <vscale x 2 x i64> %b
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}
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; Undefined lane insert
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define <vscale x 8 x half> @test_lane9_8xf16(<vscale x 8 x half> %a) {
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; CHECK-LABEL: test_lane9_8xf16
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; CHECK: mov w[[IDXREG:.*]], #9
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; CHECK: index z[[CMPVEC:[0-9]+]].h, #0, #1
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; CHECK: mov z[[IDXVEC:[0-9]+]].h, w[[IDXREG]]
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; CHECK: cmpeq p[[PRED:[0-9]+]].h, p{{[0-7]}}/z, z[[CMPVEC]].h, z[[IDXVEC]].h
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; CHECK: fmov h[[VALREG:[0-9]+]], #1.00000000
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; CHECK: mov z0.h, p[[PRED]]/m, h[[VALREG]]
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%b = insertelement <vscale x 8 x half> %a, half 1.0, i32 9
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ret <vscale x 8 x half> %b
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}
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define <vscale x 16 x i8> @test_lane1_16xi8(<vscale x 16 x i8> %a) {
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; CHECK-LABEL: test_lane1_16xi8
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; CHECK: mov w[[IDXREG:.*]], #1
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; CHECK: index z[[CMPVEC:[0-9]+]].b, #0, #1
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; CHECK: mov z[[IDXVEC:[0-9]+]].b, w[[IDXREG]]
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; CHECK: cmpeq p[[PRED:[0-9]+]].b, p{{[0-7]}}/z, z[[CMPVEC]].b, z[[IDXVEC]].b
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; CHECK: mov w[[VALREG:.*]], #30
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; CHECK: mov z0.b, p[[PRED]]/m, w[[VALREG]]
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%b = insertelement <vscale x 16 x i8> %a, i8 30, i32 1
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ret <vscale x 16 x i8> %b
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}
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define <vscale x 16 x i8> @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) {
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; CHECK-LABEL: test_lanex_16xi8
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; CHECK: index z[[CMPVEC:[0-9]+]].b, #0, #1
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; CHECK: mov z[[IDXVEC:[0-9]+]].b, w[[IDXREG]]
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; CHECK: cmpeq p[[PRED:[0-9]+]].b, p{{[0-7]}}/z, z[[CMPVEC]].b, z[[IDXVEC]].b
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; CHECK: mov w[[VALREG:.*]], #30
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; CHECK: mov z0.b, p[[PRED]]/m, w[[VALREG]]
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%b = insertelement <vscale x 16 x i8> %a, i8 30, i32 %x
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ret <vscale x 16 x i8> %b
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}
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; Redundant lane insert
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define <vscale x 4 x i32> @extract_insert_4xi32(<vscale x 4 x i32> %a) {
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; CHECK-LABEL: extract_insert_4xi32
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; CHECK-NOT: mov w{{.*}}, #30
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; CHECK-NOT: mov z0.d
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%b = extractelement <vscale x 4 x i32> %a, i32 2
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%c = insertelement <vscale x 4 x i32> %a, i32 %b, i32 2
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ret <vscale x 4 x i32> %c
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}
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define <vscale x 8 x i16> @test_lane6_undef_8xi16(i16 %a) {
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; CHECK-LABEL: test_lane6_undef_8xi16
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; CHECK: mov w[[IDXREG:.*]], #6
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; CHECK: index z[[CMPVEC:.*]].h, #0, #1
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; CHECK: mov z[[IDXVEC:[0-9]+]].h, w[[IDXREG]]
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; CHECK: cmpeq p[[PRED:.*]].h, p{{.*}}/z, z[[CMPVEC]].h, z[[IDXVEC]].h
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; CHECK: mov z0.h, p[[PRED]]/m, w0
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%b = insertelement <vscale x 8 x i16> undef, i16 %a, i32 6
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ret <vscale x 8 x i16> %b
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}
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define <vscale x 16 x i8> @test_lane0_undef_16xi8(i8 %a) {
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; CHECK-LABEL: test_lane0_undef_16xi8
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; CHECK: fmov s0, w0
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%b = insertelement <vscale x 16 x i8> undef, i8 %a, i32 0
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ret <vscale x 16 x i8> %b
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}
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