074b802654
This should be directly implied from the register class, and there's no need to special case live ins here. This was getting the wrong answer for the queue ptr argument in callable functions, since it's not an explicit IR argument and is always uniform. Fixes not using scalar loads for the aperture in addrspacecast lowering, and any other places that use implicit SGPR arguments.
367 lines
15 KiB
LLVM
367 lines
15 KiB
LLVM
; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
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; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; CI: enable_sgpr_queue_ptr = 1
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; GFX9: enable_sgpr_queue_ptr = 0
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; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
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; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
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; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
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; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], -1
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; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
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; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
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; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]]
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; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base
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; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], -1
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; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
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; At most 2 digits. Make sure src_shared_base is not counted as a high
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; number SGPR.
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; CI: NumSgprs: {{[0-9][0-9]+}}
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; GFX9: NumSgprs: {{[0-9]+}}
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define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 {
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%stof = addrspacecast i32 addrspace(3)* %ptr to i32*
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store volatile i32 7, i32* %stof
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ret void
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}
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; Test handling inside a non-kernel
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; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast_func:
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; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
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; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
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; CI-DAG: v_cmp_ne_u32_e32 vcc, -1, v0
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; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0
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; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
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; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_SHARED_BASE]]
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; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_shared_base
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; GFX9-DAG: v_cmp_ne_u32_e32 vcc, -1, v0
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; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0, vcc
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; GFX9-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
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define void @use_group_to_flat_addrspacecast_func(i32 addrspace(3)* %ptr) #0 {
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%stof = addrspacecast i32 addrspace(3)* %ptr to i32*
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store volatile i32 7, i32* %stof
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ret void
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}
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; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; CI: enable_sgpr_queue_ptr = 1
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; GFX9: enable_sgpr_queue_ptr = 0
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; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
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; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}}
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; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
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; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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; CI-DAG: v_cmp_ne_u32_e64 vcc, [[PTR]], 0
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; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
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; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
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; GFX9-DAG: s_lshl_b32 [[SSRC_PRIVATE_BASE:s[0-9]+]], [[SSRC_PRIVATE]], 16
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; GFX9-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[SSRC_PRIVATE_BASE]]
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; GFX9-XXX: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], src_private_base
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; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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; GFX9: v_cmp_ne_u32_e64 vcc, [[PTR]], 0
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; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
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; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
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; CI: NumSgprs: {{[0-9][0-9]+}}
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; GFX9: NumSgprs: {{[0-9]+}}
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define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 {
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%stof = addrspacecast i32 addrspace(5)* %ptr to i32*
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store volatile i32 7, i32* %stof
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ret void
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}
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; no-op
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; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast:
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
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; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
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define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 {
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%stof = addrspacecast i32 addrspace(1)* %ptr to i32*
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store volatile i32 7, i32* %stof
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ret void
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}
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; no-op
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; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
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; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
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; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
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define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 {
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%stof = addrspacecast i32 addrspace(4)* %ptr to i32*
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%ld = load volatile i32, i32* %stof
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ret void
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}
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; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
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; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
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; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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; HSA: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
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define amdgpu_kernel void @use_constant_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 {
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%stof = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)*
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%ld = load volatile i32, i32 addrspace(1)* %stof
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ret void
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}
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; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}
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; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}}
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; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
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; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
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; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
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; HSA: ds_write_b32 [[CASTPTR]], v[[K]]
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define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 {
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%ftos = addrspacecast i32* %ptr to i32 addrspace(3)*
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store volatile i32 0, i32 addrspace(3)* %ftos
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ret void
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}
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; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}
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; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}}
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; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
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; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], 0, v[[VPTR_LO]]
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; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
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; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 {
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%ftos = addrspacecast i32* %ptr to i32 addrspace(5)*
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store volatile i32 0, i32 addrspace(5)* %ftos
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ret void
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}
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; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast:
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
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; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0
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; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
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define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 {
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%ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
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store volatile i32 0, i32 addrspace(1)* %ftos
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ret void
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}
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; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast:
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
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; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0
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define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 {
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%ftos = addrspacecast i32* %ptr to i32 addrspace(4)*
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load volatile i32, i32 addrspace(4)* %ftos
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ret void
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}
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; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast:
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; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
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; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
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; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
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; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
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; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]]
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; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base
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; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
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define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 {
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%cast = addrspacecast i32 addrspace(3)* null to i32*
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store volatile i32 7, i32* %cast
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ret void
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}
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; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast:
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; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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; HSA: ds_write_b32 [[PTR]], [[K]]
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define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 {
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%cast = addrspacecast i32* null to i32 addrspace(3)*
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store volatile i32 7, i32 addrspace(3)* %cast
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ret void
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}
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; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast:
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; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
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define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 {
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%cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32*
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store volatile i32 7, i32* %cast
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ret void
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}
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; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast:
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; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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; HSA: ds_write_b32 [[PTR]], [[K]]
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define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 {
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%cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(3)*
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store volatile i32 7, i32 addrspace(3)* %cast
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ret void
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}
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; FIXME: Shouldn't need to enable queue ptr
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; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast:
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; CI: enable_sgpr_queue_ptr = 1
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; GFX9: enable_sgpr_queue_ptr = 0
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; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
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define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
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%cast = addrspacecast i32 addrspace(5)* null to i32*
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store volatile i32 7, i32* %cast
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ret void
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}
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; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast:
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; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0
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define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
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%cast = addrspacecast i32* null to i32 addrspace(5)*
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store volatile i32 7, i32 addrspace(5)* %cast
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ret void
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}
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; Disable optimizations in case there are optimizations added that
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; specialize away generic pointer accesses.
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; HSA-LABEL: {{^}}branch_use_flat_i32:
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; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}
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; HSA: s_endpgm
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define amdgpu_kernel void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
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entry:
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%cmp = icmp ne i32 %c, 0
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br i1 %cmp, label %local, label %global
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local:
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%flat_local = addrspacecast i32 addrspace(3)* %lptr to i32*
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br label %end
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global:
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%flat_global = addrspacecast i32 addrspace(1)* %gptr to i32*
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br label %end
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end:
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%fptr = phi i32* [ %flat_local, %local ], [ %flat_global, %global ]
|
|
store volatile i32 %x, i32* %fptr, align 4
|
|
; %val = load i32, i32* %fptr, align 4
|
|
; store i32 %val, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; Check for prologue initializing special SGPRs pointing to scratch.
|
|
; HSA-LABEL: {{^}}store_flat_scratch:
|
|
; CI-DAG: s_mov_b32 flat_scratch_lo, s9
|
|
; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11
|
|
; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8
|
|
|
|
; GFX9: s_add_u32 flat_scratch_lo, s6, s9
|
|
; GFX9: s_addc_u32 flat_scratch_hi, s7, 0
|
|
|
|
; HSA: {{flat|global}}_store_dword
|
|
; HSA: s_barrier
|
|
; HSA: {{flat|global}}_load_dword
|
|
define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
|
|
%alloca = alloca i32, i32 9, align 4, addrspace(5)
|
|
%x = call i32 @llvm.amdgcn.workitem.id.x() #2
|
|
%pptr = getelementptr i32, i32 addrspace(5)* %alloca, i32 %x
|
|
%fptr = addrspacecast i32 addrspace(5)* %pptr to i32*
|
|
store volatile i32 %x, i32* %fptr
|
|
; Dummy call
|
|
call void @llvm.amdgcn.s.barrier() #1
|
|
%reload = load volatile i32, i32* %fptr, align 4
|
|
store volatile i32 %reload, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast
|
|
; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
|
|
; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
|
|
; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}}
|
|
; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
|
|
; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
|
|
; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}}
|
|
define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(i8 addrspace(4)* addrspace(4)* %ptr.ptr, i32 %offset) #0 {
|
|
%ptr = load volatile i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %ptr.ptr
|
|
%addrspacecast = addrspacecast i8 addrspace(4)* %ptr to i8 addrspace(6)*
|
|
%gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset
|
|
%ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)*
|
|
%load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4
|
|
ret void
|
|
}
|
|
|
|
; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast
|
|
; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
|
|
; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
|
|
; GFX9: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}, [[PTRPTR]], 0x0{{$}}
|
|
; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
|
|
; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
|
|
; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x0{{$}}
|
|
define amdgpu_kernel void @use_global_to_constant32_addrspacecast(i8 addrspace(1)* addrspace(4)* %ptr.ptr, i32 %offset) #0 {
|
|
%ptr = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* %ptr.ptr
|
|
%addrspacecast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(6)*
|
|
%gep = getelementptr i8, i8 addrspace(6)* %addrspacecast, i32 %offset
|
|
%ptr.cast = bitcast i8 addrspace(6)* %gep to i32 addrspace(6)*
|
|
%load = load volatile i32, i32 addrspace(6)* %ptr.cast, align 4
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.amdgcn.s.barrier() #1
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #2
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind convergent }
|
|
attributes #2 = { nounwind readnone }
|