3fa5ee67ba
At the moment, SME-to-LLVM lowerings rely entirely on `LLVMTypeConverter`. This patch introduces a dedicated `TypeConverter` that inherits from `LLVMTypeConverter` (it will also be used when lowering ArmSME Ops to LLVM). The new type converter merely disables lowerings for `VectorType` to prevent 2-d scalable vectors (common in the context of ArmSME), e.g. `vector<[16]x[16]xi8>`, entering the LLVM Type converter. LLVM does not support arrays of scalable vectors and hence the need for specialisation. In the case of SME such types are effectively eliminated when emitting LLVM IR intrinsics for SME. Differential Revision: https://reviews.llvm.org/D155365
129 lines
5.1 KiB
C++
129 lines
5.1 KiB
C++
//===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
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#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
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#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
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#include "mlir/Dialect/AMX/AMXDialect.h"
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#include "mlir/Dialect/AMX/Transforms.h"
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#include "mlir/Dialect/Arith/IR/Arith.h"
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#include "mlir/Dialect/ArmNeon/ArmNeonDialect.h"
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#include "mlir/Dialect/ArmSME/IR/ArmSME.h"
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#include "mlir/Dialect/ArmSME/Transforms/Passes.h"
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#include "mlir/Dialect/ArmSME/Transforms/Transforms.h"
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#include "mlir/Dialect/ArmSVE/ArmSVEDialect.h"
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#include "mlir/Dialect/ArmSVE/Transforms.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/Vector/Transforms/LoweringPatterns.h"
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#include "mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h"
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#include "mlir/Dialect/X86Vector/Transforms.h"
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#include "mlir/Dialect/X86Vector/X86VectorDialect.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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namespace mlir {
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#define GEN_PASS_DEF_CONVERTVECTORTOLLVMPASS
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#include "mlir/Conversion/Passes.h.inc"
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} // namespace mlir
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using namespace mlir;
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using namespace mlir::vector;
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namespace {
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struct LowerVectorToLLVMPass
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: public impl::ConvertVectorToLLVMPassBase<LowerVectorToLLVMPass> {
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using Base::Base;
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// Override explicitly to allow conditional dialect dependence.
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void getDependentDialects(DialectRegistry ®istry) const override {
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registry.insert<LLVM::LLVMDialect>();
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registry.insert<arith::ArithDialect>();
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registry.insert<memref::MemRefDialect>();
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if (armNeon)
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registry.insert<arm_neon::ArmNeonDialect>();
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if (armSVE)
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registry.insert<arm_sve::ArmSVEDialect>();
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if (armSME)
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registry.insert<arm_sme::ArmSMEDialect>();
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if (amx)
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registry.insert<amx::AMXDialect>();
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if (x86Vector)
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registry.insert<x86vector::X86VectorDialect>();
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}
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void runOnOperation() override;
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};
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} // namespace
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void LowerVectorToLLVMPass::runOnOperation() {
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// Perform progressive lowering of operations on slices and
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// all contraction operations. Also applies folding and DCE.
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{
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RewritePatternSet patterns(&getContext());
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populateVectorToVectorCanonicalizationPatterns(patterns);
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populateVectorBroadcastLoweringPatterns(patterns);
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populateVectorContractLoweringPatterns(patterns, VectorTransformsOptions());
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populateVectorMaskOpLoweringPatterns(patterns);
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populateVectorShapeCastLoweringPatterns(patterns);
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populateVectorTransposeLoweringPatterns(patterns,
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VectorTransformsOptions());
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// Vector transfer ops with rank > 1 should be lowered with VectorToSCF.
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populateVectorTransferLoweringPatterns(patterns, /*maxTransferRank=*/1);
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(void)applyPatternsAndFoldGreedily(getOperation(), std::move(patterns));
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}
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// Convert to the LLVM IR dialect.
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LowerToLLVMOptions options(&getContext());
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options.useOpaquePointers = useOpaquePointers;
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LLVMTypeConverter converter(&getContext(), options);
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RewritePatternSet patterns(&getContext());
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populateVectorMaskMaterializationPatterns(patterns, force32BitVectorIndices);
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populateVectorTransferLoweringPatterns(patterns);
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populateVectorToLLVMMatrixConversionPatterns(converter, patterns);
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populateVectorToLLVMConversionPatterns(
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converter, patterns, reassociateFPReductions, force32BitVectorIndices);
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populateVectorToLLVMMatrixConversionPatterns(converter, patterns);
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// Architecture specific augmentations.
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LLVMConversionTarget target(getContext());
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target.addLegalDialect<arith::ArithDialect>();
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target.addLegalDialect<memref::MemRefDialect>();
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target.addLegalOp<UnrealizedConversionCastOp>();
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arm_sme::ArmSMETypeConverter armSMEConverter(&getContext(), options);
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if (armNeon) {
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// TODO: we may or may not want to include in-dialect lowering to
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// LLVM-compatible operations here. So far, all operations in the dialect
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// can be translated to LLVM IR so there is no conversion necessary.
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target.addLegalDialect<arm_neon::ArmNeonDialect>();
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}
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if (armSVE) {
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configureArmSVELegalizeForExportTarget(target);
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populateArmSVELegalizeForLLVMExportPatterns(converter, patterns);
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}
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if (armSME) {
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configureArmSMELegalizeForExportTarget(target);
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populateArmSMELegalizeForLLVMExportPatterns(armSMEConverter, patterns);
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}
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if (amx) {
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configureAMXLegalizeForExportTarget(target);
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populateAMXLegalizeForLLVMExportPatterns(converter, patterns);
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}
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if (x86Vector) {
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configureX86VectorLegalizeForExportTarget(target);
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populateX86VectorLegalizeForLLVMExportPatterns(converter, patterns);
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}
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if (failed(
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applyPartialConversion(getOperation(), target, std::move(patterns))))
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signalPassFailure();
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}
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