e6a4ba3aa6
- When an unconditional branch is expanded into an indirect branch, if there is no scavenged register, an SGPR pair needs spilling to enable the destination PC calculation. In addition, before jumping into the destination, that clobbered SGPR pair need restoring. - As SGPR cannot be spilled to or restored from memory directly, the spilling/restoring of that SGPR pair reuses the regular SGPR spilling support but without spilling it into memory. As that spilling and restoring points are fully controlled, we only need to spill that SGPR into the temporary VGPR, which needs spilling into its emergency slot. - The target-specific hook is revised to take additional restore block, where the restoring code is filled. After that, the relaxation will place that restore block directly before the destination block and insert an unconditional branch in any fall-through block into the destination block. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D106449
579 lines
17 KiB
C++
579 lines
17 KiB
C++
//===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AVR implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRInstrInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "AVR.h"
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#include "AVRMachineFunctionInfo.h"
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#include "AVRRegisterInfo.h"
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#include "AVRTargetMachine.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "AVRGenInstrInfo.inc"
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namespace llvm {
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AVRInstrInfo::AVRInstrInfo()
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: AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
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void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const DebugLoc &DL, MCRegister DestReg,
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MCRegister SrcReg, bool KillSrc) const {
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const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
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const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
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unsigned Opc;
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// Not all AVR devices support the 16-bit `MOVW` instruction.
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if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
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if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else {
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Register DestLo, DestHi, SrcLo, SrcHi;
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TRI.splitReg(DestReg, DestLo, DestHi);
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TRI.splitReg(SrcReg, SrcLo, SrcHi);
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// Copy each individual register with the `MOV` instruction.
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BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
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.addReg(SrcLo, getKillRegState(KillSrc));
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BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
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.addReg(SrcHi, getKillRegState(KillSrc));
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}
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} else {
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if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
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Opc = AVR::MOVRdRr;
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} else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
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Opc = AVR::SPREAD;
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} else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
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Opc = AVR::SPWRITE;
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} else {
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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BuildMI(MBB, MI, DL, get(Opc), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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}
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unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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case AVR::LDDRdPtrQ:
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case AVR::LDDWRdYQ: { //: FIXME: remove this once PR13375 gets fixed
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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break;
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}
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default:
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break;
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}
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return 0;
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}
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unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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case AVR::STDPtrQRr:
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case AVR::STDWPtrQRr: {
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if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
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MI.getOperand(1).getImm() == 0) {
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FrameIndex = MI.getOperand(0).getIndex();
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return MI.getOperand(2).getReg();
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}
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break;
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}
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default:
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break;
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}
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return 0;
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}
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void AVRInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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Register SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
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AFI->setHasSpills(true);
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DebugLoc DL;
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if (MI != MBB.end()) {
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DL = MI->getDebugLoc();
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}
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FrameIndex),
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MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlign(FrameIndex));
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unsigned Opcode = 0;
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if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
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Opcode = AVR::STDPtrQRr;
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} else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
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Opcode = AVR::STDWPtrQRr;
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} else {
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llvm_unreachable("Cannot store this register into a stack slot!");
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}
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BuildMI(MBB, MI, DL, get(Opcode))
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addReg(SrcReg, getKillRegState(isKill))
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.addMemOperand(MMO);
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}
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void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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Register DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (MI != MBB.end()) {
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DL = MI->getDebugLoc();
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}
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MachineFunction &MF = *MBB.getParent();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FrameIndex),
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MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlign(FrameIndex));
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unsigned Opcode = 0;
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if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
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Opcode = AVR::LDDRdPtrQ;
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} else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
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// Opcode = AVR::LDDWRdPtrQ;
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//: FIXME: remove this once PR13375 gets fixed
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Opcode = AVR::LDDWRdYQ;
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} else {
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llvm_unreachable("Cannot load this register from a stack slot!");
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}
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BuildMI(MBB, MI, DL, get(Opcode), DestReg)
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addMemOperand(MMO);
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}
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const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
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switch (CC) {
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default:
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llvm_unreachable("Unknown condition code!");
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case AVRCC::COND_EQ:
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return get(AVR::BREQk);
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case AVRCC::COND_NE:
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return get(AVR::BRNEk);
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case AVRCC::COND_GE:
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return get(AVR::BRGEk);
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case AVRCC::COND_LT:
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return get(AVR::BRLTk);
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case AVRCC::COND_SH:
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return get(AVR::BRSHk);
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case AVRCC::COND_LO:
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return get(AVR::BRLOk);
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case AVRCC::COND_MI:
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return get(AVR::BRMIk);
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case AVRCC::COND_PL:
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return get(AVR::BRPLk);
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}
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}
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AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default:
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return AVRCC::COND_INVALID;
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case AVR::BREQk:
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return AVRCC::COND_EQ;
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case AVR::BRNEk:
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return AVRCC::COND_NE;
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case AVR::BRSHk:
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return AVRCC::COND_SH;
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case AVR::BRLOk:
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return AVRCC::COND_LO;
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case AVR::BRMIk:
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return AVRCC::COND_MI;
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case AVR::BRPLk:
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return AVRCC::COND_PL;
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case AVR::BRGEk:
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return AVRCC::COND_GE;
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case AVR::BRLTk:
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return AVRCC::COND_LT;
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}
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}
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AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
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switch (CC) {
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default:
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llvm_unreachable("Invalid condition!");
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case AVRCC::COND_EQ:
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return AVRCC::COND_NE;
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case AVRCC::COND_NE:
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return AVRCC::COND_EQ;
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case AVRCC::COND_SH:
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return AVRCC::COND_LO;
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case AVRCC::COND_LO:
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return AVRCC::COND_SH;
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case AVRCC::COND_GE:
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return AVRCC::COND_LT;
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case AVRCC::COND_LT:
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return AVRCC::COND_GE;
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case AVRCC::COND_MI:
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return AVRCC::COND_PL;
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case AVRCC::COND_PL:
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return AVRCC::COND_MI;
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}
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}
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bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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MachineBasicBlock::iterator I = MBB.end();
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MachineBasicBlock::iterator UnCondBrIter = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugInstr()) {
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continue;
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}
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// Working from the bottom, when we see a non-terminator
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// instruction, we're done.
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if (!isUnpredicatedTerminator(*I)) {
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break;
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}
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// A terminator that isn't a branch can't easily be handled
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// by this analysis.
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if (!I->getDesc().isBranch()) {
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return true;
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}
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// Handle unconditional branches.
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//: TODO: add here jmp
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if (I->getOpcode() == AVR::RJMPk) {
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UnCondBrIter = I;
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// If the block has any instructions after a JMP, delete them.
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while (std::next(I) != MBB.end()) {
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std::next(I)->eraseFromParent();
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}
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Cond.clear();
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FBB = 0;
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// Delete the JMP if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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UnCondBrIter = MBB.end();
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continue;
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}
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// TBB is used to indicate the unconditinal destination.
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// Handle conditional branches.
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AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
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if (BranchCode == AVRCC::COND_INVALID) {
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return true; // Can't handle indirect branch.
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}
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// Working from the bottom, handle the first conditional branch.
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if (Cond.empty()) {
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MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
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if (AllowModify && UnCondBrIter != MBB.end() &&
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MBB.isLayoutSuccessor(TargetBB)) {
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// If we can modify the code and it ends in something like:
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//
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// jCC L1
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// jmp L2
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// L1:
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// ...
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// L2:
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//
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// Then we can change this to:
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//
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// jnCC L2
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// L1:
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// ...
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// L2:
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//
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// Which is a bit more efficient.
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// We conditionally jump to the fall-through block.
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BranchCode = getOppositeCondition(BranchCode);
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unsigned JNCC = getBrCond(BranchCode).getOpcode();
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MachineBasicBlock::iterator OldInst = I;
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
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.addMBB(UnCondBrIter->getOperand(0).getMBB());
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
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.addMBB(TargetBB);
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OldInst->eraseFromParent();
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UnCondBrIter->eraseFromParent();
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// Restart the analysis.
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UnCondBrIter = MBB.end();
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I = MBB.end();
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continue;
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}
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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continue;
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}
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// Handle subsequent conditional branches. Only handle the case where all
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// conditional branches branch to the same destination.
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assert(Cond.size() == 1);
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assert(TBB);
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// Only handle the case where all conditional branches branch to
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// the same destination.
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if (TBB != I->getOperand(0).getMBB()) {
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return true;
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}
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AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
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// If the conditions are the same, we can leave them alone.
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if (OldBranchCode == BranchCode) {
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continue;
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}
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return true;
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}
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return false;
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}
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unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL, int *BytesAdded) const {
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if (BytesAdded)
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*BytesAdded = 0;
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// Shouldn't be a fall through.
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assert(TBB && "insertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"AVR branch conditions have one component!");
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if (Cond.empty()) {
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assert(!FBB && "Unconditional branch with multiple successors!");
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auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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return 1;
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}
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// Conditional branch.
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unsigned Count = 0;
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AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
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auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(CondMI);
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++Count;
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if (FBB) {
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// Two-way Conditional branch. Insert the second branch.
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auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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++Count;
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}
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return Count;
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}
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unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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if (BytesRemoved)
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*BytesRemoved = 0;
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugInstr()) {
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continue;
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}
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//: TODO: add here the missing jmp instructions once they are implemented
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// like jmp, {e}ijmp, and other cond branches, ...
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if (I->getOpcode() != AVR::RJMPk &&
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getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
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break;
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}
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// Remove the branch.
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if (BytesRemoved)
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*BytesRemoved += getInstSizeInBytes(*I);
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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bool AVRInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1 && "Invalid AVR branch condition!");
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AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm());
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Cond[0].setImm(getOppositeCondition(CC));
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return false;
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}
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unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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// A regular instruction
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default: {
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const MCInstrDesc &Desc = get(Opcode);
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return Desc.getSize();
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}
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case TargetOpcode::EH_LABEL:
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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case TargetOpcode::DBG_VALUE:
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return 0;
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case TargetOpcode::INLINEASM:
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case TargetOpcode::INLINEASM_BR: {
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const MachineFunction &MF = *MI.getParent()->getParent();
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|
const AVRTargetMachine &TM =
|
|
static_cast<const AVRTargetMachine &>(MF.getTarget());
|
|
const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
|
|
const TargetInstrInfo &TII = *STI.getInstrInfo();
|
|
|
|
return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
|
|
*TM.getMCAsmInfo());
|
|
}
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
AVRInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
llvm_unreachable("unexpected opcode!");
|
|
case AVR::JMPk:
|
|
case AVR::CALLk:
|
|
case AVR::RCALLk:
|
|
case AVR::RJMPk:
|
|
case AVR::BREQk:
|
|
case AVR::BRNEk:
|
|
case AVR::BRSHk:
|
|
case AVR::BRLOk:
|
|
case AVR::BRMIk:
|
|
case AVR::BRPLk:
|
|
case AVR::BRGEk:
|
|
case AVR::BRLTk:
|
|
return MI.getOperand(0).getMBB();
|
|
case AVR::BRBSsk:
|
|
case AVR::BRBCsk:
|
|
return MI.getOperand(1).getMBB();
|
|
case AVR::SBRCRrB:
|
|
case AVR::SBRSRrB:
|
|
case AVR::SBICAb:
|
|
case AVR::SBISAb:
|
|
llvm_unreachable("unimplemented branch instructions");
|
|
}
|
|
}
|
|
|
|
bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
|
|
int64_t BrOffset) const {
|
|
|
|
switch (BranchOp) {
|
|
default:
|
|
llvm_unreachable("unexpected opcode!");
|
|
case AVR::JMPk:
|
|
case AVR::CALLk:
|
|
return true;
|
|
case AVR::RCALLk:
|
|
case AVR::RJMPk:
|
|
return isIntN(13, BrOffset);
|
|
case AVR::BRBSsk:
|
|
case AVR::BRBCsk:
|
|
case AVR::BREQk:
|
|
case AVR::BRNEk:
|
|
case AVR::BRSHk:
|
|
case AVR::BRLOk:
|
|
case AVR::BRMIk:
|
|
case AVR::BRPLk:
|
|
case AVR::BRGEk:
|
|
case AVR::BRLTk:
|
|
return isIntN(7, BrOffset);
|
|
}
|
|
}
|
|
|
|
void AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
|
|
MachineBasicBlock &NewDestBB,
|
|
MachineBasicBlock &RestoreBB,
|
|
const DebugLoc &DL, int64_t BrOffset,
|
|
RegScavenger *RS) const {
|
|
// This method inserts a *direct* branch (JMP), despite its name.
|
|
// LLVM calls this method to fixup unconditional branches; it never calls
|
|
// insertBranch or some hypothetical "insertDirectBranch".
|
|
// See lib/CodeGen/RegisterRelaxation.cpp for details.
|
|
// We end up here when a jump is too long for a RJMP instruction.
|
|
BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
|
|
|
|
return;
|
|
}
|
|
|
|
} // end of namespace llvm
|