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clang-p2996/llvm/lib/Target/RISCV
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jacquesguan 6405e8b584 [RISCV] Refactor some rvv instructions' definition with foreach. 
Simplify rvv instructions that use eew in their mnemonic and encoding with foreach. And fix a scheduling bug.

Differential Revision: https://reviews.llvm.org/D113453
2021-11-16 15:20:45 +08:00
..
AsmParser
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
Disassembler
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
MCTargetDesc
[RISCV] Optimize immediate materialisation with SH*ADD
2021-11-15 23:34:28 +00:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
CMakeLists.txt
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCV.h
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCV.td
[RISCV] Support Zfhmin extension
2021-11-06 01:41:02 +08:00
RISCVAsmPrinter.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"
2021-10-02 10:44:11 -07:00
RISCVFrameLowering.cpp
[RISCV] Fix invalid kill on callee save
2021-11-02 11:56:54 +00:00
RISCVFrameLowering.h
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
RISCVGatherScatterLowering.cpp
[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
2021-10-27 19:33:48 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Teach needVSETVLIPHI to handle mask register instructions.
2021-11-15 09:57:28 -08:00
RISCVInstrFormats.td
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.
2021-10-28 11:39:04 +08:00
RISCVInstrInfo.h
[amdgpu] Handle the case where there is no scavenged register.
2021-10-27 18:37:27 -04:00
RISCVInstrInfo.td
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
RISCVInstrInfoA.td
…
RISCVInstrInfoC.td
…
RISCVInstrInfoD.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoF.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoM.td
[RISCV] Improve codegen for i32 udiv/urem by constant on RV64.
2021-11-12 14:49:10 -08:00
RISCVInstrInfoV.td
[RISCV] Refactor some rvv instructions' definition with foreach.
2021-11-16 15:20:45 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
RISCVInstrInfoZb.td
[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.
2021-10-14 09:25:03 -07:00
RISCVInstrInfoZfh.td
[RISCV] Support Zfhmin extension
2021-11-06 01:41:02 +08:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.
2021-11-04 10:08:01 -07:00
RISCVISelDAGToDAG.h
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
RISCVISelLowering.cpp
[RISCV] Override TargetLowering::hasAndNot for Zbb.
2021-11-15 18:44:07 -08:00
RISCVISelLowering.h
[RISCV] Override TargetLowering::hasAndNot for Zbb.
2021-11-15 18:44:07 -08:00
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
…
RISCVMCInstLower.cpp
[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
2021-08-04 10:39:50 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Remove unused member variable. NFC
2021-10-14 12:56:47 -07:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Sync Zvlsseg register order as the same as vector registers.
2021-10-28 13:34:53 +08:00
RISCVSchedRocket.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSchedSiFive7.td
[RISCV] Fix typo in RISCVSchedSiFive7.td
2021-09-01 16:39:48 -05:00
RISCVSchedule.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVScheduleB.td
…
RISCVScheduleV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp
[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
2021-10-27 19:33:48 -07:00
RISCVSubtarget.h
[RISCV] Support Zfhmin extension
2021-11-06 01:41:02 +08:00
RISCVSystemOperands.td
[RISCV] Add vcsr CSR name for V extension.
2021-10-25 08:56:25 -07:00
RISCVTargetMachine.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
2021-10-27 19:33:48 -07:00
RISCVTargetTransformInfo.h
[RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI
2021-10-27 19:33:48 -07:00