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clang-p2996/llvm/test/Analysis/CostModel/X86
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Roman Lebedev 7114c60e8f [NFC][X86][Costmodel] Improve test coverage for {i8,i16,i32,i64}->i1 vector trunc
2021-11-15 20:46:48 +03:00
..
abs.ll
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aggregates.ll
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alternate-shuffle-cost.ll
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arith-fix.ll
[X86][Costmodel] trunc v32i16 to v64i8 can appear after legalization, cost is same as for trunc v32i16 to v32i8
2021-11-15 19:04:02 +03:00
arith-fma.ll
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arith-fp.ll
[CostModel][X86] Improve AVX512 FDIV costs
2021-06-06 21:41:05 +01:00
arith-overflow.ll
[X86][Costmodel] trunc v32i16 to v64i8 can appear after legalization, cost is same as for trunc v32i16 to v32i8
2021-11-15 19:04:02 +03:00
arith-sminmax.ll
[CostModel][TTI] Replace BAD_ICMP_PREDICATE with ICMP_SGT/UGT for generic abs/min/max cost expansion
2021-10-08 12:41:58 +01:00
arith-ssat.ll
[CostModel][TTI] Replace BAD_ICMP_PREDICATE with ICMP_SGT for generic sadd/ssub sat cost expansion
2021-10-07 15:42:45 +01:00
arith-uminmax.ll
[CostModel][TTI] Replace BAD_ICMP_PREDICATE with ICMP_SGT/UGT for generic abs/min/max cost expansion
2021-10-08 12:41:58 +01:00
arith-usat.ll
[CostModel][TTI] Replace BAD_ICMP_PREDICATE with ICMP_ULT/UGT for generic uadd/usubo cost expansion
2021-10-06 19:11:32 +01:00
arith.ll
[X86][Costmodel] trunc v32i16 to v64i8 can appear after legalization, cost is same as for trunc v32i16 to v32i8
2021-11-15 19:04:02 +03:00
bitreverse.ll
[CostModel][X86] Adjust bitreverse/ctpop/ctlz/cttz AVX2+ costs based on llvm-mca reports
2021-09-15 13:04:40 +01:00
bswap-store.ll
[X86] Improve costmodel for scalar byte swaps
2021-05-08 15:17:35 +03:00
bswap-vec.ll
[CostModel][X86] Add 512-bit bswap costs
2021-06-06 22:36:34 +01:00
bswap.ll
[X86] Improve costmodel for scalar byte swaps
2021-05-08 15:17:35 +03:00
cast.ll
[CostModel][X86] Improve AVX1/AVX2 v16i32->v16i16/v16i8 truncation costs (PR51972)
2021-09-26 13:43:46 +01:00
costmodel.ll
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ctlz.ll
[CostModel][X86] Adjust bitreverse/ctpop/ctlz/cttz AVX2+ costs based on llvm-mca reports
2021-09-15 13:04:40 +01:00
ctpop.ll
[CostModel][X86] Adjust bitreverse/ctpop/ctlz/cttz AVX2+ costs based on llvm-mca reports
2021-09-15 13:04:40 +01:00
cttz.ll
[CostModel][X86] Adjust bitreverse/ctpop/ctlz/cttz AVX2+ costs based on llvm-mca reports
2021-09-15 13:04:40 +01:00
div.ll
[CostModel][X86] Add div/rem by negative power-of-2 constants
2021-10-17 18:51:15 +01:00
extend.ll
[NFC][X86][Costmodel] Improve test coverage for i1->{i8,i16,i32,i64} vector *ext
2021-11-15 20:46:48 +03:00
fcmp.ll
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fmaxnum-size-latency.ll
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fmaxnum.ll
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fminnum-size-latency.ll
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fminnum.ll
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fptosi.ll
[CostModel][X86] Adjust fptosi/fptoui SSE/AVX legalized costs based on llvm-mca reports.
2021-07-12 20:38:25 +01:00
fptoui.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
free-intrinsics.ll
[Tests] Fix incorrect noalias metadata
2021-09-18 20:51:00 +02:00
fround.ll
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fshl.ll
[CostModel][TTI] Replace BAD_ICMP_PREDICATE with ICMP_EQ for generic funnel shift cost expansion
2021-10-06 16:39:16 +01:00
fshr.ll
[CostModel][TTI] Replace BAD_ICMP_PREDICATE with ICMP_EQ for generic funnel shift cost expansion
2021-10-06 16:39:16 +01:00
gather-i8-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
gather-i16-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
gather-i32-with-i8-index.ll
[X86][LV] X86 does *not* prefer vectorized addressing
2021-10-16 12:32:18 +03:00
gather-i64-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
gep.ll
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i32.ll
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icmp.ll
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insert-extract-at-zero-inseltpoison.ll
[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack
2021-07-05 13:26:53 +01:00
insert-extract-at-zero.ll
[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack
2021-07-05 13:26:53 +01:00
interleave-load-i32.ll
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interleave-store-i32.ll
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interleaved-load-f32-stride-2.ll
[TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 interleaved load costs
2021-10-16 16:21:45 +01:00
interleaved-load-f32-stride-3.ll
[X86][Costmodel] Load/store i32 Stride=3 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-load-f32-stride-4.ll
[X86][Costmodel] Load/store i32 Stride=4 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-load-f32-stride-6.ll
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs
2021-10-05 16:58:58 +03:00
interleaved-load-f64-stride-2.ll
[X86][Costmodel] Load/store i64 Stride=2 VF=32 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-load-f64-stride-3.ll
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs
2021-10-04 14:35:17 +03:00
interleaved-load-f64-stride-4.ll
[X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-load-f64-stride-6.ll
[X86][Costmodel] Load/store i64/f64 Stride=6 VF=8 interleaving costs
2021-10-05 16:58:58 +03:00
interleaved-load-float.ll
[X86][Costmodel] Load/store i32/f32 Stride=3 VF=8 interleaving costs
2021-10-04 14:34:05 +03:00
interleaved-load-half.ll
[NFC][X86] New Test Requires Asserts
2021-08-10 10:22:04 +01:00
interleaved-load-i8-stride-2.ll
[X86][Costmodel] Load/store i8 Stride=2 VF=32 interleaving costs
2021-09-29 21:52:45 +03:00
interleaved-load-i8-stride-3.ll
[X86][Costmodel] Load/store i8 Stride=3 VF=32 interleaving costs
2021-10-02 13:39:15 +03:00
interleaved-load-i8-stride-4.ll
[X86][Costmodel] Load/store i8 Stride=4 VF=32 interleaving costs
2021-10-02 13:40:21 +03:00
interleaved-load-i8-stride-6.ll
[X86][Costmodel] Load/store i8 Stride=6 VF=32 interleaving costs
2021-10-03 23:39:22 +03:00
interleaved-load-i16-stride-2.ll
[TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs
2021-10-16 17:28:07 +01:00
interleaved-load-i16-stride-3.ll
[X86][Costmodel] Load/store i16 Stride=3 VF=32 interleaving costs
2021-10-03 23:40:35 +03:00
interleaved-load-i16-stride-4.ll
[TTI] BasicTTI::getInterleavedMemoryOpCost(): use getScalarizationOverhead()
2021-09-29 16:41:53 +01:00
interleaved-load-i16-stride-5.ll
[X86][LV] X86 does *not* prefer vectorized addressing
2021-10-16 12:32:18 +03:00
interleaved-load-i16-stride-6.ll
[X86][Costmodel] Load/store i16 Stride=6 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-load-i32-stride-2-indices-0u.ll
[X86] X86TTIImpl::getInterleavedMemoryOpCost(): scale interleaving cost by the fraction of live members
2021-10-22 16:33:58 +03:00
interleaved-load-i32-stride-2.ll
[TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 interleaved load costs
2021-10-16 16:21:45 +01:00
interleaved-load-i32-stride-3-indices-0uu.ll
[X86] X86TTIImpl::getInterleavedMemoryOpCost(): scale interleaving cost by the fraction of live members
2021-10-22 16:33:58 +03:00
interleaved-load-i32-stride-3-indices-01u.ll
[X86] X86TTIImpl::getInterleavedMemoryOpCost(): scale interleaving cost by the fraction of live members
2021-10-22 16:33:58 +03:00
interleaved-load-i32-stride-3.ll
[X86][Costmodel] Load/store i32 Stride=3 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-load-i32-stride-4-indices-0uuu.ll
[X86] X86TTIImpl::getInterleavedMemoryOpCost(): scale interleaving cost by the fraction of live members
2021-10-22 16:33:58 +03:00
interleaved-load-i32-stride-4-indices-01uu.ll
[X86] X86TTIImpl::getInterleavedMemoryOpCost(): scale interleaving cost by the fraction of live members
2021-10-22 16:33:58 +03:00
interleaved-load-i32-stride-4-indices-012u.ll
[X86] X86TTIImpl::getInterleavedMemoryOpCost(): scale interleaving cost by the fraction of live members
2021-10-22 16:33:58 +03:00
interleaved-load-i32-stride-4.ll
[X86][Costmodel] Load/store i32 Stride=4 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-load-i32-stride-6.ll
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs
2021-10-05 16:58:58 +03:00
interleaved-load-i64-stride-2.ll
[X86][Costmodel] Load/store i64 Stride=2 VF=32 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-load-i64-stride-3.ll
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs
2021-10-04 14:35:17 +03:00
interleaved-load-i64-stride-4.ll
[X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-load-i64-stride-6.ll
[X86][Costmodel] Load/store i64/f64 Stride=6 VF=8 interleaving costs
2021-10-05 16:58:58 +03:00
interleaved-store-accesses-with-gaps.ll
[X86][Costmodel] getReplicationShuffleCost(): promote 8 bit-wide elements to 32 bit when no AVX512VBMI
2021-11-15 19:04:02 +03:00
interleaved-store-f32-stride-2.ll
[X86][Costmodel] Add SSE2 sub-128bit vXi32/f32 stride 2 interleaved store costs
2021-10-18 13:46:10 +01:00
interleaved-store-f32-stride-3.ll
[X86][Costmodel] Load/store i32 Stride=3 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-store-f32-stride-4.ll
[X86][Costmodel] Load/store i32 Stride=4 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-store-f32-stride-6.ll
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs
2021-10-05 16:58:58 +03:00
interleaved-store-f64-stride-2.ll
[X86][Costmodel] Load/store i64 Stride=2 VF=32 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-store-f64-stride-3.ll
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs
2021-10-04 14:35:17 +03:00
interleaved-store-f64-stride-4.ll
[X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-store-f64-stride-6.ll
[X86][Costmodel] Load/store i64/f64 Stride=6 VF=8 interleaving costs
2021-10-05 16:58:58 +03:00
interleaved-store-i8-stride-2.ll
[X86][Costmodel] Add SSE2 sub-128bit vXi8/16 stride 2 interleaved store costs
2021-10-18 13:15:14 +01:00
interleaved-store-i8-stride-3.ll
[X86][Costmodel] Load/store i8 Stride=3 VF=8 interleaving costs
2021-10-02 13:39:15 +03:00
interleaved-store-i8-stride-4.ll
[X86][Costmodel] Load/store i8 Stride=4 VF=16 interleaving costs
2021-10-02 13:40:21 +03:00
interleaved-store-i8-stride-6.ll
[X86][Costmodel] Load/store i8 Stride=6 VF=32 interleaving costs
2021-10-03 23:39:22 +03:00
interleaved-store-i16-stride-2.ll
[X86][Costmodel] Add SSE2 sub-128bit vXi8/16 stride 2 interleaved store costs
2021-10-18 13:15:14 +01:00
interleaved-store-i16-stride-3.ll
[X86][Costmodel] Load/store i16 Stride=3 VF=32 interleaving costs
2021-10-03 23:40:35 +03:00
interleaved-store-i16-stride-4.ll
[TTI] BasicTTI::getInterleavedMemoryOpCost(): use getScalarizationOverhead()
2021-09-29 16:41:53 +01:00
interleaved-store-i16-stride-5.ll
[X86][LV] X86 does *not* prefer vectorized addressing
2021-10-16 12:32:18 +03:00
interleaved-store-i16-stride-6.ll
[X86][Costmodel] Load/store i16 Stride=6 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-store-i32-stride-2.ll
[X86][Costmodel] Add SSE2 sub-128bit vXi32/f32 stride 2 interleaved store costs
2021-10-18 13:46:10 +01:00
interleaved-store-i32-stride-3.ll
[X86][Costmodel] Load/store i32 Stride=3 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-store-i32-stride-4.ll
[X86][Costmodel] Load/store i32 Stride=4 VF=32 interleaving costs
2021-10-17 17:28:09 +03:00
interleaved-store-i32-stride-6.ll
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs
2021-10-05 16:58:58 +03:00
interleaved-store-i64-stride-2.ll
[X86][Costmodel] Load/store i64 Stride=2 VF=32 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-store-i64-stride-3.ll
[X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs
2021-10-04 14:35:17 +03:00
interleaved-store-i64-stride-4.ll
[X86][Costmodel] Load/store i64 Stride=4 VF=16 interleaving costs
2021-10-17 17:28:10 +03:00
interleaved-store-i64-stride-6.ll
[X86][Costmodel] Load/store i64/f64 Stride=6 VF=8 interleaving costs
2021-10-05 16:58:58 +03:00
intrinsic-cost-kinds.ll
[X86][Costmodel] Fix X86TTIImpl::getGSScalarCost()
2021-10-13 22:35:39 +03:00
intrinsic-cost.ll
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lit.local.cfg
…
load_store.ll
Reland [X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again
2021-05-22 11:46:32 +03:00
load-bswap.ll
[X86] Improve costmodel for scalar byte swaps
2021-05-08 15:17:35 +03:00
logicalop.ll
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loop_v2-inseltpoison.ll
…
loop_v2.ll
…
masked-gather-i32-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-gather-i64-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-intrinsic-cost-inseltpoison.ll
[X86][Costmodel] Fix X86TTIImpl::getGSScalarCost()
2021-10-13 22:35:39 +03:00
masked-intrinsic-cost.ll
[X86][Costmodel] Fix X86TTIImpl::getGSScalarCost()
2021-10-13 22:35:39 +03:00
masked-load-i8.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-load-i16.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-load-i32.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-load-i64.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-scatter-i32-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-scatter-i64-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-store-i8.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-store-i16.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-store-i32.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
masked-store-i64.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
min-legal-vector-width.ll
[CostModel][X86] Improve AVX1/AVX2 v16i32->v16i16/v16i8 truncation costs (PR51972)
2021-09-26 13:43:46 +01:00
mul32.ll
[CostModel][X86] Pre-SSE41 targets can use PMADDWD for sext sub-i16 -> i32
2021-10-14 12:17:40 +01:00
mul.ll
[X86][Costmodel] trunc v32i16 to v64i8 can appear after legalization, cost is same as for trunc v32i16 to v32i8
2021-11-15 19:04:02 +03:00
reduce-add.ll
…
reduce-and.ll
…
reduce-fadd.ll
[Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation
2021-07-26 17:15:43 +01:00
reduce-fmax.ll
[CostModel][X86] Add fast math tests for float reductions
2021-07-19 13:01:28 +01:00
reduce-fmin.ll
[CostModel][X86] Add fast math tests for float reductions
2021-07-19 13:01:28 +01:00
reduce-fmul.ll
[Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation
2021-07-26 17:15:43 +01:00
reduce-mul.ll
[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.
2021-07-07 13:58:27 +01:00
reduce-or.ll
…
reduce-smax.ll
[CostModel][X86] getCmpSelInstrCost - treat BAD_PREDICATEs the same as the worst case cost predicates for ICMP/FCMP instructions
2021-10-06 10:14:56 +01:00
reduce-smin.ll
[CostModel][X86] getCmpSelInstrCost - treat BAD_PREDICATEs the same as the worst case cost predicates for ICMP/FCMP instructions
2021-10-06 10:14:56 +01:00
reduce-umax.ll
[CostModel][X86] getCmpSelInstrCost - treat BAD_PREDICATEs the same as the worst case cost predicates for ICMP/FCMP instructions
2021-10-06 10:14:56 +01:00
reduce-umin.ll
[CostModel][X86] getCmpSelInstrCost - treat BAD_PREDICATEs the same as the worst case cost predicates for ICMP/FCMP instructions
2021-10-06 10:14:56 +01:00
reduce-xor.ll
…
reduction.ll
[TTI] Remove IsPairwiseForm from getArithmeticReductionCost
2021-07-09 11:51:16 +01:00
rem.ll
[X86][Costmodel] trunc v32i16 to v64i8 can appear after legalization, cost is same as for trunc v32i16 to v32i8
2021-11-15 19:04:02 +03:00
scalarize.ll
…
scatter-i8-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
scatter-i16-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
scatter-i32-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
scatter-i64-with-i8-index.ll
[NFC][LV][X86] Improve test coverage for masked mem ops
2021-10-27 13:36:04 +03:00
shuffle-broadcast-fp16.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
shuffle-broadcast.ll
…
shuffle-extract_subvector.ll
…
shuffle-insert_subvector.ll
[CostModel] Treat 'widen subvector' patterns as zero cost
2021-08-02 11:43:10 +01:00
shuffle-replication-i1.ll
[NFC][X86][Costmodel] Add i1 replication shuffle costmodel test coverage
2021-11-15 20:02:52 +03:00
shuffle-replication-i8.ll
[X86][Costmodel] getReplicationShuffleCost(): promote 8 bit-wide elements to 32 bit when no AVX512VBMI
2021-11-15 19:04:02 +03:00
shuffle-replication-i16.ll
[X86][Costmodel] getReplicationShuffleCost(): promote 16 bit-wide elements to 32 bit when no AVX512BW
2021-11-14 20:01:38 +03:00
shuffle-replication-i32.ll
[X86][Costmodel] getReplicationShuffleCost(): implement cost model for 32/64 bit-wide elements with AVX512F
2021-11-10 22:52:33 +03:00
shuffle-replication-i64.ll
[X86][Costmodel] getReplicationShuffleCost(): implement cost model for 32/64 bit-wide elements with AVX512F
2021-11-10 22:52:33 +03:00
shuffle-reverse-fp16.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
shuffle-reverse.ll
[COST][X86]Improve cost model for reverse shuffle v32i16/v64i8 in AVX512F.
2021-04-27 11:14:21 -07:00
shuffle-select.ll
…
shuffle-single-src-fp16.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
shuffle-single-src.ll
…
shuffle-transpose.ll
…
shuffle-two-src-fp16.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
shuffle-two-src.ll
…
sitofp.ll
[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.
2021-07-07 13:58:27 +01:00
size-cost.ll
…
slm-arith-costs.ll
[CostModel][X86] Adjust vXi32 multiply costs if it can be performed using PMADDWD
2021-09-25 16:28:48 +01:00
sse-itoi.ll
[CostModel][X86] Adjust truncate SSE/AVX legalized costs based on llvm-mca reports.
2021-07-12 13:50:43 +01:00
strided-load-i8.ll
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strided-load-i16.ll
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strided-load-i32.ll
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strided-load-i64.ll
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tiny.ll
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trunc.ll
[NFC][X86][Costmodel] Improve test coverage for {i8,i16,i32,i64}->i1 vector trunc
2021-11-15 20:46:48 +03:00
uitofp.ll
[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.
2021-07-07 13:58:27 +01:00
uniformshift-inseltpoison.ll
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uniformshift.ll
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vdiv-cost.ll
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vector_gep-inseltpoison.ll
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vector_gep.ll
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vector-extract.ll
[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack
2021-07-05 13:26:53 +01:00
vector-insert-inseltpoison.ll
[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack
2021-07-05 13:26:53 +01:00
vector-insert.ll
[CostModel][X86] Handle costs for insert/extractelement with non-immediate indices via stack
2021-07-05 13:26:53 +01:00
vectorized-loop.ll
[CostModel][X86] Improve v8i32 MUL costs on AVX1 targets to account for slower btver2
2021-05-22 11:13:07 +01:00
vselect-cost.ll
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vshift-ashr-cost-inseltpoison.ll
[CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.
2021-07-22 20:07:32 +01:00
vshift-ashr-cost.ll
[CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.
2021-07-22 20:07:32 +01:00
vshift-lshr-cost-inseltpoison.ll
[CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.
2021-07-22 20:07:32 +01:00
vshift-lshr-cost.ll
[CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.
2021-07-22 20:07:32 +01:00
vshift-shl-cost-inseltpoison.ll
[CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.
2021-07-22 20:07:32 +01:00
vshift-shl-cost.ll
[CostModel][X86] Adjust shift SSE4 legalized costs based on llvm-mca reports.
2021-07-22 20:07:32 +01:00