152072801e
The root of the buildvector can have only one use, otherwise it can be treated only as a final element of the previous buildvector sequence.
77 lines
4.1 KiB
LLVM
77 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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;RUN: opt -S -slp-vectorizer -mtriple=x86_64-unknown-linux-android23 < %s | FileCheck %s
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define void @test() {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr undef, i32 2
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 4
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; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
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; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x float> undef, float [[TMP8]], i64 0
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; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 0
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; CHECK-NEXT: store <2 x float> zeroinitializer, ptr null, align 4
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; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
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; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x float> [[TMP9]], float [[TMP11]], i64 0
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; CHECK-NEXT: store <2 x float> zeroinitializer, ptr null, align 4
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; CHECK-NEXT: ret void
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;
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%1 = getelementptr inbounds float, ptr undef, i32 2
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%2 = load float, ptr %1, align 4
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%3 = load float, ptr undef, align 4
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%4 = fsub float %2, %3
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%5 = getelementptr inbounds float, ptr undef, i32 3
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%6 = load float, ptr %5, align 4
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%7 = getelementptr inbounds float, ptr undef, i32 1
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%8 = load float, ptr %7, align 4
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%9 = fsub float %6, %8
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%10 = fcmp olt float %9, %4
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%11 = insertelement <2 x float> undef, float %3, i64 0
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%12 = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 0
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store <2 x float> zeroinitializer, ptr null, align 4
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%13 = insertelement <2 x float> %11, float %6, i64 0
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store <2 x float> zeroinitializer, ptr null, align 4
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ret void
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}
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define void @test1() {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr undef, i32 2
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 4
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; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x float> [[TMP3]], i32 0
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; CHECK-NEXT: [[DOTSROA_0_0_VEC_INSERT_I5_I10:%.*]] = insertelement <2 x float> undef, float [[TMP8]], i64 0
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; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP3]], i32 1
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; CHECK-NEXT: [[DOTSROA_0_4_VEC_INSERT_I10_I13:%.*]] = insertelement <2 x float> [[DOTSROA_0_0_VEC_INSERT_I5_I10]], float [[TMP9]], i64 1
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; CHECK-NEXT: store <2 x float> [[DOTSROA_0_4_VEC_INSERT_I10_I13]], ptr null, align 4
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
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; CHECK-NEXT: [[DOTSROA_0_4_VEC_INSERT_I10_I13_2:%.*]] = insertelement <2 x float> [[DOTSROA_0_0_VEC_INSERT_I5_I10]], float [[TMP10]], i64 1
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; CHECK-NEXT: store <2 x float> [[DOTSROA_0_4_VEC_INSERT_I10_I13_2]], ptr null, align 4
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; CHECK-NEXT: ret void
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;
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%1 = getelementptr inbounds float, ptr undef, i32 2
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%2 = load float, ptr %1, align 4
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%3 = load float, ptr undef, align 4
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%4 = fsub float %2, %3
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%5 = getelementptr inbounds float, ptr undef, i32 3
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%6 = load float, ptr %5, align 4
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%7 = getelementptr inbounds float, ptr undef, i32 1
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%8 = load float, ptr %7, align 4
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%9 = fsub float %6, %8
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%10 = fcmp olt float %9, %4
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%.sroa.0.0.vec.insert.i5.i10 = insertelement <2 x float> undef, float %3, i64 0
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%.sroa.0.4.vec.insert.i10.i13 = insertelement <2 x float> %.sroa.0.0.vec.insert.i5.i10, float %8, i64 1
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store <2 x float> %.sroa.0.4.vec.insert.i10.i13, ptr null, align 4
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%.sroa.0.4.vec.insert.i10.i13.2 = insertelement <2 x float> %.sroa.0.0.vec.insert.i5.i10, float %6, i64 1
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store <2 x float> %.sroa.0.4.vec.insert.i10.i13.2, ptr null, align 4
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ret void
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}
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