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clang-p2996/llvm/test/CodeGen/Hexagon
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Brendon Cahoon 65b6ebccad [Pipeliner] Fix an asssert due to invalid Phi in the epilog 
The pipeliner was generating an invalid Phi name for an operand
in the epilog block, which caused an assert in the live variable
analysis pass. The fix is to the code that generates new Phis
in the epilog block. In this case, there is an existing Phi that
needs to be reused rather than creating a new Phi instruction.

Differential Revision: https://reviews.llvm.org/D23513

llvm-svn: 278805
2016-08-16 14:29:24 +00:00
..
intrinsics
[Hexagon] Add support for __builtin_prefetch
2016-02-18 13:58:38 +00:00
vect
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
absaddr-store.ll
[Hexagon] Fix printing the address operand of S2_storerinewabs
2016-04-19 20:20:33 +00:00
absimm.ll
[Hexagon] Fixing store instructions and reenabling a few more tests.
2015-11-10 00:22:00 +00:00
adde.ll
[Hexagon] Enable the post-RA scheduler
2016-05-26 19:44:28 +00:00
addh-sext-trunc.ll
…
addh-shifted.ll
…
addh.ll
…
addr-calc-opt.ll
[Hexagon] Improve balancing of address calculation
2016-07-29 15:15:35 +00:00
addrmode-indoff.ll
…
alu64.ll
[Hexagon] Preprocess mapped instructions before lowering to MC
2015-12-15 17:05:45 +00:00
always-ext.ll
[Hexagon] Fixing load instruction parsing and reenabling tests.
2015-11-10 00:02:27 +00:00
args.ll
…
ashift-left-right.ll
…
Atomics.ll
[Hexagon] Handle expansion of cmpxchg
2016-06-22 16:07:10 +00:00
avoid-predspill-calleesaved.ll
[Hexagon] Optimize stack slot spills
2016-02-12 22:53:35 +00:00
avoid-predspill.ll
[Hexagon] Optimize stack slot spills
2016-02-12 22:53:35 +00:00
barrier-flag.ll
…
base-offset-addr.ll
…
base-offset-post.ll
…
bit-eval.ll
[Hexagon] Preprocess mapped instructions before lowering to MC
2015-12-15 17:05:45 +00:00
bit-extractu-half.ll
[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
2016-01-14 21:59:22 +00:00
bit-gen-rseq.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
bit-loop-rc-mismatch.ll
[Hexagon] Gracefully handle reg class mismatch in HexagonLoopReschedule
2016-07-26 19:17:13 +00:00
bit-loop.ll
[Hexagon] Bit-based instruction simplification
2015-10-20 22:57:13 +00:00
bit-phi.ll
[Hexagon] Do not insert non-phis before phis in bit simplification
2016-01-13 15:48:18 +00:00
bit-rie.ll
[Hexagon] Rerun bit tracker on new instructions in RIE
2016-07-26 19:08:45 +00:00
bit-skip-byval.ll
[Hexagon] Skip byval arguments when checking parameter attributes
2016-08-11 18:15:16 +00:00
bit-validate-reg.ll
[Hexagon] Validate register class when doing bit simplification
2016-08-04 17:56:19 +00:00
bitconvert-vector.ll
[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)
2016-06-27 15:08:22 +00:00
block-addr.ll
[Hexagon] Treat all conditional branches as predicted (not-taken by default)
2016-05-09 18:22:07 +00:00
block-ranges-nodef.ll
[Hexagon] Properly close live range in HexagonBlockRanges ---add testcase
2016-04-22 17:30:13 +00:00
branch-non-mbb.ll
[Hexagon] Handle branches with non-mbb operands
2016-01-14 15:05:27 +00:00
BranchPredict.ll
…
brev_ld.ll
[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
2016-02-12 17:01:51 +00:00
brev_st.ll
[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
2016-02-12 17:01:51 +00:00
bugAsmHWloop.ll
…
builtin-prefetch-offset.ll
[Hexagon] Add support for __builtin_prefetch
2016-02-18 13:58:38 +00:00
builtin-prefetch.ll
[Hexagon] Add support for __builtin_prefetch
2016-02-18 13:58:38 +00:00
calling-conv-2.ll
…
callr-dep-edge.ll
[ScheduleDAG] Make sure to process all def operands before any use operands
2016-05-10 16:50:30 +00:00
cext-check.ll
[Hexagon] Simplify HexagonInstrInfo::isPredicable
2016-05-16 16:56:10 +00:00
cext-valid-packet1.ll
…
cext-valid-packet2.ll
…
cext.ll
…
cexti16.ll
…
cfi-late.ll
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
2016-04-15 15:57:41 +00:00
cfi-offset.ll
[Hexagon] Use offsets relative to FP+8 in .cfi_offset instructions
2016-05-11 14:53:07 +00:00
checktabs.ll
…
circ_ld.ll
[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
2016-02-12 17:01:51 +00:00
circ_ldd_bug.ll
…
circ_ldw.ll
…
circ_st.ll
[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
2016-02-12 17:01:51 +00:00
circ-load-isel.ll
[Hexagon] Remove dead nodes from SelectionDAG to avoid cycles
2016-05-13 18:48:15 +00:00
clr_set_toggle.ll
[Hexagon] Improve patterns with stack-based addressing
2016-07-15 15:35:52 +00:00
cmp_pred2.ll
…
cmp_pred_reg.ll
…
cmp_pred.ll
…
cmp-extend.ll
…
cmp-promote.ll
…
cmp-to-genreg.ll
…
cmp-to-predreg.ll
…
cmp.ll
Revert r265817
2016-04-08 18:15:37 +00:00
cmpb_pred.ll
…
cmpb-eq.ll
…
combine_ir.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
combine.ll
[Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors
2016-08-03 18:35:48 +00:00
common-gep-basic.ll
…
common-gep-icm.ll
…
compound.ll
[Hexagon] Fixing compound register printing and reenabling more tests.
2015-11-10 00:51:56 +00:00
const64.ll
[Hexagon] Generate CONST64 when optimizing for size in copy-to-combine
2016-01-15 14:08:31 +00:00
const-pool-tf.ll
[Hexagon] Improve test to check for @PCREL, only run llc, not opt -> llc.
2016-08-16 13:10:09 +00:00
constp-clb.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
constp-combine-neg.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
constp-ctb.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
constp-extract.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
constp-physreg.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
constp-rewrite-branches.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
constp-rseq.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
constp-vsplat.ll
[Hexagon] Implement MI-level constant propagation
2016-07-28 20:01:59 +00:00
convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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csr-func-usedef.ll
[Hexagon] Register save/restore functions do not follow regular conventions
2016-04-25 17:49:44 +00:00
ctlz-cttz-ctpop.ll
…
ctor.ll
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dadd.ll
…
dmul.ll
…
double.ll
…
doubleconvert-ieee-rnd-near.ll
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dsub.ll
…
dualstore.ll
…
duplex.ll
…
early-if-conversion-bug1.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
early-if-phi-i1.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
early-if-spare.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
early-if-vecpi.ll
[Hexagon] Post-increment loads/stores enhancements
2016-07-26 20:30:30 +00:00
early-if.ll
[Hexagon] Add an early if-conversion pass
2015-10-06 15:49:14 +00:00
eh_return.ll
…
eliminate-pred-spill.ll
[Hexagon] HexagonMachineScheduler should account for resources
2016-07-18 14:52:13 +00:00
expand-condsets-basic.ll
…
expand-condsets-pred-undef.ll
[Hexagon] Teach mux expansion how to deal with undef predicates
2016-04-22 16:47:01 +00:00
expand-condsets-rm-segment.ll
…
expand-condsets-undef.ll
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extload-combine.ll
[Hexagon] Expand handling of the small-data/bss section
2016-04-21 18:56:45 +00:00
extract-basic.ll
…
fadd.ll
…
fcmp.ll
…
float.ll
…
floatconvert-ieee-rnd-near.ll
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fmul.ll
…
frame-offset-overflow.ll
[Hexagon] Check for offset overflow when reserving scavenging slots
2016-08-01 17:15:30 +00:00
frame.ll
…
fsel.ll
[Hexagon] Use integer instructions for floating point immediates
2016-08-10 16:46:36 +00:00
fsub.ll
…
fusedandshift.ll
…
gp-plus-offset-load.ll
[Hexagon] Missed testcase update in r260895
2016-02-15 16:15:02 +00:00
gp-plus-offset-store.ll
…
gp-rel.ll
…
hwloop1.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
hwloop2.ll
…
hwloop3.ll
…
hwloop4.ll
…
hwloop5.ll
…
hwloop-cleanup.ll
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hwloop-const.ll
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hwloop-crit-edge.ll
[LSR] Don't try and create post-inc expressions on non-rotated loops
2016-08-15 07:53:03 +00:00
hwloop-dbg.ll
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
2016-04-15 15:57:41 +00:00
hwloop-le.ll
…
hwloop-loop1.ll
[LSR] Don't try and create post-inc expressions on non-rotated loops
2016-08-15 07:53:03 +00:00
hwloop-lt1.ll
…
hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-noreturn-call.ll
[Hexagon] Allow non-returning calls in hardware loops
2016-08-11 21:14:25 +00:00
hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preh.ll
[Hexagon] Find speculative loop preheader in hardware loop generation
2016-07-27 21:20:54 +00:00
hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
…
hwloop-wrap2.ll
…
hwloop-wrap.ll
…
i1_VarArg.ll
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
2015-11-25 20:30:59 +00:00
i8_VarArg.ll
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
2015-11-25 20:30:59 +00:00
i16_VarArg.ll
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
2015-11-25 20:30:59 +00:00
idxload-with-zero-offset.ll
…
ifcvt-diamond-bad.ll
Proper handling of diamond-like cases in if-conversion
2016-01-20 13:14:52 +00:00
ifcvt-edge-weight.ll
Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
2015-12-01 05:29:22 +00:00
ifcvt-impuse-livein.mir
If-conversion incorrectly calculates liveness of redefined registers
2016-08-11 18:42:06 +00:00
indirect-br.ll
…
inline-asm-hexagon.ll
[Hexagon] Add support for proper handling of H and L constraints
2016-07-26 17:31:02 +00:00
inline-asm-qv.ll
[Hexagon] Recognize "q" and "v" in inline-asm as register constraints
2016-05-18 14:34:51 +00:00
insert4.ll
[Hexagon] Expand pseudo instruction Insert4
2016-01-14 15:37:16 +00:00
insert-basic.ll
…
is-legal-void.ll
[Hexagon] Do not check alignment for unsized types in isLegalAddressingMode
2016-08-03 15:06:18 +00:00
lit.local.cfg
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loadi1-G0.ll
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loadi1-v4-G0.ll
…
loadi1-v4.ll
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loadi1.ll
…
long-calls.ll
[Hexagon] Add target feature to generate long calls
2016-07-25 14:42:11 +00:00
loop-prefetch.ll
[Hexagon] Use loop data prefetch on Hexagon
2016-07-22 14:22:43 +00:00
lower-extract-subvector.ll
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
2016-07-29 16:44:27 +00:00
macint.ll
…
maxd.ll
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maxh.ll
…
maxud.ll
…
maxuw.ll
…
maxw.ll
…
mem-fi-add.ll
Revert "Change memcpy/memset/memmove to have dest and source alignments."
2015-11-19 05:56:52 +00:00
memcpy-likely-aligned.ll
[Hexagon] Make memcpy lowering thread-safe
2015-12-16 17:29:37 +00:00
memops1.ll
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memops2.ll
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memops3.ll
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memops-stack.ll
[Hexagon] Improve patterns with stack-based addressing
2016-07-15 15:35:52 +00:00
memops.ll
[Hexagon] Improve patterns with stack-based addressing
2016-07-15 15:35:52 +00:00
mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
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minud.ll
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minuw.ll
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minw.ll
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misaligned_double_vector_store_not_fast.ll
[Hexagon] Fix test that uses -debug-only to require asserts.
2016-07-29 21:44:33 +00:00
misaligned-access.ll
…
misched-top-rptracker-sync.ll
Reset the TopRPTracker's position in ScheduleDAGMILive::initQueues
2016-04-28 19:17:44 +00:00
mpy.ll
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mulhs.ll
[Hexagon] Add pattern for 64-bit mulhs
2016-08-08 19:24:25 +00:00
mux-basic.ll
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newvaluejump2.ll
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newvaluejump.ll
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newvaluestore.ll
[Hexagon] Enable the post-RA scheduler
2016-05-26 19:44:28 +00:00
NVJumpCmp.ll
[Hexagon] Add NewValueJump support for C4_cmpneq, C4_cmplte, C4_cmplteu
2015-12-08 16:28:32 +00:00
opt-addr-mode.ll
[Hexagon] Optimize addressing modes for load/store
2016-04-29 15:49:13 +00:00
opt-fabs.ll
[Hexagon] Bit-based instruction simplification
2015-10-20 22:57:13 +00:00
opt-fneg.ll
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opt-spill-volatile.ll
[Hexagon] Do not optimize volatile stack spill slots
2016-07-27 20:50:42 +00:00
packetize_cond_inst.ll
…
packetize-cfi-location.ll
[Hexagon] Insert CFI instructions before throwing calls
2016-07-28 19:13:46 +00:00
packetize-tailcall-arg.ll
[Hexagon] Packetize function call arguments with tail call instructions
2016-07-14 19:30:55 +00:00
peephole-kill-flags.ll
[Hexagon] Clear kill flags from modified registers in peephole optimizer
2016-08-04 14:17:16 +00:00
peephole-op-swap.ll
[Hexagon] Fix operand swapping in HexagonPeephole
2016-04-19 21:36:24 +00:00
pic-jumptables.ll
[Hexagon] Add PIC support
2015-12-18 20:19:30 +00:00
pic-local.ll
Start using shouldAssumeDSOLocal on Hexagon.
2016-06-22 19:09:14 +00:00
pic-regusage.ll
[Hexagon] Generate PIC-specific versions of save/restore routines
2016-03-24 19:18:48 +00:00
pic-simple.ll
[Hexagon] Add PIC support
2015-12-18 20:19:30 +00:00
pic-static.ll
[Hexagon] Add PIC support
2015-12-18 20:19:30 +00:00
postinc-load.ll
…
postinc-offset.ll
[Hexagon] Implement RDF-based post-RA optimizations
2016-01-12 19:09:01 +00:00
postinc-store.ll
…
pred-absolute-store.ll
…
pred-gp.ll
…
pred-instrs.ll
…
predicate-copy.ll
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predicate-logical.ll
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predicate-rcmp.ll
…
propagate-vcombine.ll
[Hexagon] Recognize vcombine in copy propagation
2016-08-02 21:49:20 +00:00
rdf-copy-undef2.ll
[RDF] Handle undefined registers in RDF copy propagation
2016-04-28 15:09:19 +00:00
rdf-copy.ll
Codegen: Tail Merge: Be less aggressive with special cases.
2016-08-10 18:36:18 +00:00
rdf-dead-loop.ll
[Hexagon] Implement RDF-based post-RA optimizations
2016-01-12 19:09:01 +00:00
rdf-inline-asm-fixed.ll
[RDF] Improve handling of inline-asm
2016-04-28 20:33:33 +00:00
rdf-inline-asm.ll
[RDF] Improve handling of inline-asm
2016-04-28 20:33:33 +00:00
rdf-reset-kills.ll
[RDF] Consider register as live if any alias is live
2016-04-20 14:33:23 +00:00
reg-scavengebug-3.ll
[Hexagon] Optimize stack slot spills
2016-02-12 22:53:35 +00:00
reg-scavenger-valid-slot.ll
When looking for a spill slot in reg scavenger, find one that matches RC
2016-05-18 18:16:00 +00:00
relax.ll
Revert r265817
2016-04-08 18:15:37 +00:00
remove_lsr.ll
…
remove-endloop.ll
…
restore-single-reg.ll
[Hexagon] Only use restore functions for single register at -Oz
2016-03-28 14:52:21 +00:00
ret-struct-by-val.ll
[Hexagon] Handle returning small structures by value
2016-07-18 17:30:41 +00:00
runtime-stkchk.ll
[Hexagon] Add support for run-time stack overflow checking
2016-03-24 20:20:07 +00:00
sdata-array.ll
[Hexagon] Expand handling of the small-data/bss section
2016-04-21 18:56:45 +00:00
sdata-basic.ll
[Hexagon] Expand handling of the small-data/bss section
2016-04-21 18:56:45 +00:00
sdr-basic.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
sdr-shr32.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
section_7275.ll
[Hexagon] Expand handling of the small-data/bss section
2016-04-21 18:56:45 +00:00
select-instr-align.ll
[Hexagon] Improve handling of unaligned vector loads and stores
2016-03-28 15:43:03 +00:00
sf-min-max.ll
[Hexagon] Add extra patterns for single-precision min/max instructions
2016-08-10 17:56:24 +00:00
shrink-frame-basic.ll
…
signed_immediates.ll
…
simple_addend.ll
[Hexagon] Delay emission of CFI instructions
2015-10-19 17:46:01 +00:00
simpletailcall.ll
…
split-const32-const64.ll
[Hexagon] Simplify the SplitConst32/64 pass
2016-08-10 18:05:47 +00:00
stack-align1.ll
…
stack-align2.ll
…
stack-alloca1.ll
…
stack-alloca2.ll
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static.ll
[Hexagon] Expand handling of the small-data/bss section
2016-04-21 18:56:45 +00:00
store-shift.ll
[Hexagon] Add SDAG preprocessing step to expose shifted addressing modes
2016-06-22 20:08:27 +00:00
store-widen-aliased-load.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
store-widen-negv2.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
store-widen-negv.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
store-widen.ll
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
storerd-io-over-rr.ll
[Hexagon] Prefer _io over _rr for 64-bit store with constant offset
2016-08-02 18:50:05 +00:00
storerinewabs.ll
[Hexagon] Fix printing the address operand of S2_storerinewabs
2016-04-19 20:20:33 +00:00
struct_args_large.ll
The canonical way to XFAIL a test for all targets is XFAIL: *, not XFAIL:
2016-02-04 16:21:38 +00:00
struct_args.ll
[Hexagon] Bitwise operations for insert/extract word not simplified
2016-07-26 18:30:11 +00:00
sube.ll
[Hexagon] Use timing class info as tie-breaker in machine scheduler
2016-07-18 15:17:10 +00:00
swp-const-tc.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-dag-phi.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-epilog-reuse-1.ll
[Pipeliner] Fix an asssert due to invalid Phi in the epilog
2016-08-16 14:29:24 +00:00
swp-epilog-reuse.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-matmul-bitext.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-max.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-multi-loops.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-vect-dotprod.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-vmult.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
swp-vsum.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
tail-call-mem-intrinsics.ll
Revert "Change memcpy/memset/memmove to have dest and source alignments."
2015-11-19 05:56:52 +00:00
tail-call-trunc.ll
…
tail-dup-subreg-abort.ll
Tail duplication can mix incompatible registers in phi nodes
2015-10-21 02:40:06 +00:00
tail-dup-subreg-map.ll
[Tail duplication] Handle source registers with subregisters
2016-04-26 18:36:34 +00:00
tfr-to-combine.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
tls_pic.ll
[Hexagon] Optimize addressing modes for load/store
2016-04-29 15:49:13 +00:00
tls_static.ll
[Hexagon] Optimize addressing modes for load/store
2016-04-29 15:49:13 +00:00
union-1.ll
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
usr-ovf-dep.ll
…
v6vec-vprint.ll
[Hexagon] Generate vector printing instructions
2016-08-01 19:36:39 +00:00
v60-cur.ll
MachinePipeliner pass that implements Swing Modulo Scheduling
2016-07-29 16:44:44 +00:00
v60Intrins.ll
[Hexagon] Enable the post-RA scheduler
2016-05-26 19:44:28 +00:00
v60small.ll
[Hexagon] Hexagon V60 HVX intrinsic defintions
2015-11-26 16:54:33 +00:00
v60Vasr.ll
[Hexagon] Adding v60 test, vasr in particular.
2015-12-07 18:52:39 +00:00
vaddh.ll
…
validate-offset.ll
…
vdmpy-halide-test.ll
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
2016-07-29 16:44:27 +00:00
vec-pred-spill1.ll
[Hexagon] Optimize stack slot spills
2016-02-12 22:53:35 +00:00
vector-align.ll
[Hexagon] Specify vector alignment in DataLayout string
2016-02-12 14:47:38 +00:00
vload-postinc-sel.ll
[Hexagon] Simplify (+fix) instruction selection for indexed loads/stores
2016-06-24 21:27:17 +00:00
vmpa-halide-test.ll
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
2016-07-29 16:44:27 +00:00
vpack_eo.ll
[Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX
2016-07-29 16:44:27 +00:00
vselect-pseudo.ll
[Hexagon] Expand VSelect pseudo instructions
2016-05-12 19:16:02 +00:00
vsplat-isel.ll
[Hexagon] Properly handle instruction selection of vsplat intrinsics
2016-05-12 17:21:40 +00:00
zextloadi1.ll
[Hexagon] Optimize addressing modes for load/store
2016-04-29 15:49:13 +00:00