a041239bb7
ppcg will be used to provide mapping decisions for GPU code generation. As we do not use C as input language, we do not include pet. However, we include pet.h from pet 82cacb71 plus a set of dummy functions to ensure ppcg links without problems. The version of ppcg committed is unmodified ppcg-0.04 which has been well tested in the context of LLVM. It does not provide an official library interface yet, which means that in upcoming commits we will add minor modifications to make necessary functionality accessible. We will aim to upstream these modifications after we gained enough experience with GPU generation support in Polly to propose a stable interface. Reviewers: Meinersbur Subscribers: pollydev, llvm-commits Differential Revision: http://reviews.llvm.org/D22033 llvm-svn: 275274
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
#ifndef GPU_ARRAY_TILE_H
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#define GPU_ARRAY_TILE_H
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#include <isl/aff_type.h>
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#include <isl/map_type.h>
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#include <isl/val.h>
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/* The fields stride and shift only contain valid information
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* if shift != NULL.
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* If so, they express that current index is such that if you add shift,
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* then the result is always a multiple of stride.
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* Let D represent the initial group->depth dimensions of the computed schedule.
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* The spaces of "lb" and "shift" are of the form
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*
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* D -> [b]
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*/
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struct gpu_array_bound {
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isl_val *size;
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isl_aff *lb;
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isl_val *stride;
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isl_aff *shift;
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};
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/* A tile of an array.
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*
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* requires_unroll is set if the schedule dimensions that are mapped
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* to threads need to be unrolled for this (private) tile to be used.
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*
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* n is the dimension of the array.
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* bound is an array of size "n" representing the lower bound
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* and size for each index.
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*
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* tiling maps a tile in the global array to the corresponding
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* shared/private memory tile and is of the form
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*
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* { [D[i] -> A[a]] -> T[(a + shift(i))/stride - lb(i)] }
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*
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* where D represents the initial group->depth dimensions
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* of the computed schedule.
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*/
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struct gpu_array_tile {
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isl_ctx *ctx;
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int requires_unroll;
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int n;
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struct gpu_array_bound *bound;
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isl_multi_aff *tiling;
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};
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struct gpu_array_tile *gpu_array_tile_create(isl_ctx *ctx, int n_index);
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struct gpu_array_tile *gpu_array_tile_free(struct gpu_array_tile *tile);
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__isl_give isl_val *gpu_array_tile_size(struct gpu_array_tile *tile);
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#endif
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