62d949766b
Add a spec for yet-to-be-implemented metadata to allow the backend to fully handle atomicrmw lowering. This is the base of an alternative to #69229, which inverts the direction to be correct by default, and extends to cover the peer device case.
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ReStructuredText
============================
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LLVM |release| Release Notes
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============================
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.. contents::
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:local:
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.. only:: PreRelease
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.. warning::
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These are in-progress notes for the upcoming LLVM |version| release.
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Release notes for previous releases can be found on
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`the Download Page <https://releases.llvm.org/download.html>`_.
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release |release|. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <https://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <https://llvm.org/>`_. If you
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have questions or comments, the `Discourse forums
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<https://discourse.llvm.org>`_ is a good place to ask
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them.
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Note that if you are reading this file from a Git checkout or the main
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LLVM web page, this document applies to the *next* release, not the current
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one. To see the release notes for a specific release, please see the `releases
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page <https://llvm.org/releases/>`_.
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Non-comprehensive list of changes in this release
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=================================================
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.. NOTE
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For small 1-3 sentence descriptions, just add an entry at the end of
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this list. If your description won't fit comfortably in one bullet
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point (e.g. maybe you would like to give an example of the
|
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functionality, or simply have a lot to talk about), see the `NOTE` below
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for adding a new subsection.
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* ...
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Update on required toolchains to build LLVM
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-------------------------------------------
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* The minimum Python version has been raised from 3.6 to 3.8 across all of LLVM.
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This enables the use of many new Python features, aligning more closely with
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modern Python best practices, and improves CI maintainability
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See `#78828 <https://github.com/llvm/llvm-project/pull/78828>`_ for more info.
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Changes to the LLVM IR
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----------------------
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* Added Memory Model Relaxation Annotations (MMRAs).
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* Added ``nusw`` and ``nuw`` flags to ``getelementptr`` instruction.
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* Renamed ``llvm.experimental.vector.reverse`` intrinsic to ``llvm.vector.reverse``.
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* Renamed ``llvm.experimental.vector.splice`` intrinsic to ``llvm.vector.splice``.
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* Renamed ``llvm.experimental.vector.interleave2`` intrinsic to ``llvm.vector.interleave2``.
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* Renamed ``llvm.experimental.vector.deinterleave2`` intrinsic to ``llvm.vector.deinterleave2``.
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* The constant expression variants of the following instructions have been
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removed:
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* ``icmp``
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* ``fcmp``
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* ``shl``
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* LLVM has switched from using debug intrinsics in textual IR to using debug
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records by default. Details of the change and instructions on how to update
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any downstream tools and tests can be found in the `migration docs
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<https://llvm.org/docs/RemoveDIsDebugInfo.html>`_.
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* Semantics of MC/DC intrinsics have been changed.
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* ``llvm.instprof.mcdc.parameters``: 3rd argument has been changed
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from bytes to bits.
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* ``llvm.instprof.mcdc.condbitmap.update``: Removed.
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* ``llvm.instprof.mcdc.tvbitmap.update``: 3rd argument has been
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removed. The next argument has been changed from byte index to bit
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index.
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Changes to LLVM infrastructure
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------------------------------
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Changes to building LLVM
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------------------------
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* LLVM now has rpmalloc version 1.4.5 in-tree, as a replacement C allocator for
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hosted toolchains. This supports several host platforms such as Mac or Unix,
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however currently only the Windows 64-bit LLVM release uses it.
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This has a great benefit in terms of build times on Windows when using ThinLTO
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linking, especially on machines with lots of cores, to an order of magnitude
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or more. Clang compilation is also improved. Please see some build timings in
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(`#91862 <https://github.com/llvm/llvm-project/pull/91862#issue-2291033962>`_)
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For more information, refer to the **LLVM_ENABLE_RPMALLOC** option in `CMake variables <https://llvm.org/docs/CMake.html#llvm-related-variables>`_.
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* The ``LLVM_ENABLE_TERMINFO`` flag has been removed. LLVM no longer depends on
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terminfo and now always uses the ``TERM`` environment variable for color
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support autodetection.
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Changes to TableGen
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-------------------
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- We can define type aliases via new keyword ``deftype``.
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Changes to Interprocedural Optimizations
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----------------------------------------
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Changes to the AArch64 Backend
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------------------------------
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* Added support for Cortex-R82AE, Cortex-A78AE, Cortex-A520AE, Cortex-A720AE,
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Cortex-A725, Cortex-X925, Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs.
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* ``-mbranch-protection=standard`` now enables FEAT_PAuth_LR by
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default when the feature is enabled. The new behaviour results
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in ``standard`` being equal to ``bti+pac-ret+pc`` when ``+pauth-lr``
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is passed as part of ``-mcpu=`` options.
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* SVE and SVE2 have been moved to the default extensions list for ARMv9.0,
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making them optional per the Arm ARM. Existing v9.0+ CPUs in the backend that
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support these extensions continue to have these features enabled by default
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when specified via ``-march=`` or an ``-mcpu=`` that supports them. The
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attribute ``"target-features"="+v9a"`` no longer implies ``"+sve"`` and
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``"+sve2"`` respectively.
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Changes to the AMDGPU Backend
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-----------------------------
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* Implemented the ``llvm.get.fpenv`` and ``llvm.set.fpenv`` intrinsics.
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* Added ``!amdgpu.no.fine.grained.memory`` and
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``!amdgpu.no.remote.memory`` metadata to control atomic behavior.
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* Implemented :ref:`llvm.get.rounding <int_get_rounding>` and :ref:`llvm.set.rounding <int_set_rounding>`
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* Removed ``llvm.amdgcn.ds.fadd``, ``llvm.amdgcn.ds.fmin`` and
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``llvm.amdgcn.ds.fmax`` intrinsics. Users should use the
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:ref:`atomicrmw <i_atomicrmw>` instruction with `fadd`, `fmin` and
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`fmax` with addrspace(3) instead.
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Changes to the ARM Backend
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--------------------------
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* Added support for Cortex-R52+ CPU.
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* FEAT_F32MM is no longer activated by default when using `+sve` on v8.6-A or greater. The feature is still available and can be used by adding `+f32mm` to the command line options.
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* armv8-r now implies only fp-armv8d16sp, rather than neon and full fp-armv8. These features are still included by default for cortex-r52. The default cpu for armv8-r is now "generic", for compatibility with variants that do not include neon, fp64, and d32.
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Changes to the AVR Backend
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--------------------------
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Changes to the DirectX Backend
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------------------------------
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Changes to the Hexagon Backend
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------------------------------
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Changes to the LoongArch Backend
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--------------------------------
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* i32 is now a native type in the datalayout string. This enables
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LoopStrengthReduce for loops with i32 induction variables, among other
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optimizations.
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Changes to the MIPS Backend
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---------------------------
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Changes to the PowerPC Backend
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------------------------------
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Changes to the RISC-V Backend
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-----------------------------
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* Added full support for the experimental Zabha (Byte and
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Halfword Atomic Memory Operations) extension.
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* Added assembler/disassembler support for the experimenatl Zalasr
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(Load-Acquire and Store-Release) extension.
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* The names of the majority of the S-prefixed (supervisor-level) extension
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names in the RISC-V profiles specification are now recognised.
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* Codegen support was added for the Zimop (May-Be-Operations) extension.
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* The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 1.0.0 Pointer Masking extensions are supported.
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* The experimental Ssqosid extension is supported.
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* Zacas is no longer experimental.
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* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension.
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* llvm-objdump now prints disassembled opcode bytes in groups of 2 or 4 bytes to
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match GNU objdump. The bytes within the groups are in big endian order.
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* Added smstateen extension to -march. CSR names for smstateen were already supported.
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* Zaamo and Zalrsc are no longer experimental.
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* Processors that enable post reg-alloc scheduling (PostMachineScheduler) by default should use the `UsePostRAScheduler` subtarget feature. Setting `PostRAScheduler = 1` in the scheduler model will have no effect on the enabling of the PostMachineScheduler.
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* Zabha is no longer experimental.
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* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
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* Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
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* ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added.
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* The default atomics mapping was changed to emit an additional trailing fence
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for sequentially consistent stores, offering compatibility with a future
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mapping using load-acquire and store-release instructions while remaining
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fully compatible with objects produced prior to this change. The mapping
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(ABI) used is recorded as an ELF attribute.
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* Ztso is no longer experimental.
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Changes to the WebAssembly Backend
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----------------------------------
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Changes to the Windows Target
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-----------------------------
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Changes to the X86 Backend
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--------------------------
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- Removed knl/knm specific ISA intrinsics: AVX512PF, AVX512ER, PREFETCHWT1,
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while assembly encoding/decoding supports are kept.
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Changes to the OCaml bindings
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-----------------------------
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Changes to the Python bindings
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------------------------------
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Changes to the C API
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--------------------
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* Added ``LLVMGetBlockAddressFunction`` and ``LLVMGetBlockAddressBasicBlock``
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functions for accessing the values in a blockaddress constant.
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* Added ``LLVMConstStringInContext2`` function, which better matches the C++
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API by using ``size_t`` for string length. Deprecated ``LLVMConstStringInContext``.
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* Added the following functions for accessing a function's prefix data:
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* ``LLVMHasPrefixData``
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* ``LLVMGetPrefixData``
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* ``LLVMSetPrefixData``
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* Added the following functions for accessing a function's prologue data:
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* ``LLVMHasPrologueData``
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* ``LLVMGetPrologueData``
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* ``LLVMSetPrologueData``
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* Deprecated ``LLVMConstNUWNeg`` and ``LLVMBuildNUWNeg``.
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* Added ``LLVMAtomicRMWBinOpUIncWrap`` and ``LLVMAtomicRMWBinOpUDecWrap`` to
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``LLVMAtomicRMWBinOp`` enum for AtomicRMW instructions.
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* Added ``LLVMCreateConstantRangeAttribute`` function for creating ConstantRange Attributes.
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* Added the following functions for creating and accessing data for CallBr instructions:
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* ``LLVMBuildCallBr``
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* ``LLVMGetCallBrDefaultDest``
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* ``LLVMGetCallBrNumIndirectDests``
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* ``LLVMGetCallBrIndirectDest``
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* The following functions for creating constant expressions have been removed,
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because the underlying constant expressions are no longer supported. Instead,
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an instruction should be created using the ``LLVMBuildXYZ`` APIs, which will
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constant fold the operands if possible and create an instruction otherwise:
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* ``LLVMConstICmp``
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* ``LLVMConstFCmp``
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* ``LLVMConstShl``
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**Note:** The following changes are due to the removal of the debug info
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intrinsics from LLVM and to the introduction of debug records into LLVM.
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They are described in detail in the `debug info migration guide <https://llvm.org/docs/RemoveDIsDebugInfo.html>`_.
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* Added the following functions to insert before the indicated instruction but
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after any attached debug records.
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* ``LLVMPositionBuilderBeforeDbgRecords``
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* ``LLVMPositionBuilderBeforeInstrAndDbgRecords``
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Same as ``LLVMPositionBuilder`` and ``LLVMPositionBuilderBefore`` except the
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insertion position is set to before the debug records that precede the target
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instruction. ``LLVMPositionBuilder`` and ``LLVMPositionBuilderBefore`` are
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unchanged.
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* Added the following functions to get/set the new non-instruction debug info format.
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They will be deprecated in the future and they are just a transition aid.
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* ``LLVMIsNewDbgInfoFormat``
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* ``LLVMSetIsNewDbgInfoFormat``
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* Added the following functions to insert a debug record (new debug info format).
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* ``LLVMDIBuilderInsertDeclareRecordBefore``
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* ``LLVMDIBuilderInsertDeclareRecordAtEnd``
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* ``LLVMDIBuilderInsertDbgValueRecordBefore``
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* ``LLVMDIBuilderInsertDbgValueRecordAtEnd``
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* Deleted the following functions that inserted a debug intrinsic (old debug info format).
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* ``LLVMDIBuilderInsertDeclareBefore``
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* ``LLVMDIBuilderInsertDeclareAtEnd``
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* ``LLVMDIBuilderInsertDbgValueBefore``
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* ``LLVMDIBuilderInsertDbgValueAtEnd``
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* Added the following functions for accessing a Target Extension Type's data:
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* ``LLVMGetTargetExtTypeName``
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* ``LLVMGetTargetExtTypeNumTypeParams``/``LLVMGetTargetExtTypeTypeParam``
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* ``LLVMGetTargetExtTypeNumIntParams``/``LLVMGetTargetExtTypeIntParam``
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Changes to the CodeGen infrastructure
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-------------------------------------
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Changes to the Metadata Info
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---------------------------------
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Changes to the Debug Info
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---------------------------------
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* LLVM has switched from using debug intrinsics internally to using debug
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records by default. This should happen transparently when using the DIBuilder
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to construct debug variable information, but will require changes for any code
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that interacts with debug intrinsics directly. Debug intrinsics will only be
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supported on a best-effort basis from here onwards; for more information, see
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the `migration docs <https://llvm.org/docs/RemoveDIsDebugInfo.html>`_.
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Changes to the LLVM tools
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---------------------------------
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* llvm-nm and llvm-objdump can now print symbol information from linked
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WebAssembly binaries, using information from exports or the "name"
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section for functions, globals and data segments. Symbol addresses and sizes
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are printed as offsets in the file, allowing for binary size analysis. Wasm
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files using reference types and GC are also supported (but also only for
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functions, globals, and data, and only for listing symbols and names).
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* llvm-ar now utilizes LLVM_DEFAULT_TARGET_TRIPLE to determine the archive format
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if it's not specified with the ``--format`` argument and cannot be inferred from
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input files.
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* llvm-ar now allows specifying COFF archive format with ``--format`` argument
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and uses it by default for COFF targets.
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* llvm-ranlib now supports ``-V`` as an alias for ``--version``.
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``-v`` (``--verbose`` in llvm-ar) has been removed.
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(`#87661 <https://github.com/llvm/llvm-project/pull/87661>`_)
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* llvm-objcopy now supports ``--set-symbol-visibility`` and
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``--set-symbols-visibility`` options for ELF input to change the
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visibility of symbols.
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* llvm-objcopy now supports ``--skip-symbol`` and ``--skip-symbols`` options
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for ELF input to skip the specified symbols when executing other options
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that can change a symbol's name, binding or visibility.
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* llvm-objcopy now supports ``--compress-sections`` to compress or decompress
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arbitrary sections not within a segment.
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(`#85036 <https://github.com/llvm/llvm-project/pull/85036>`_.)
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* llvm-profgen now supports COFF+DWARF binaries. This enables Sample-based PGO
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on Windows using Intel VTune's SEP. For details on usage, see the `end-user
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documentation for SPGO
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<https://clang.llvm.org/docs/UsersManual.html#using-sampling-profilers>`_.
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* llvm-readelf's ``-r`` output for RELR has been improved.
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(`#89162 <https://github.com/llvm/llvm-project/pull/89162>`_)
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``--raw-relr`` has been removed.
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* llvm-mca now aborts by default if it is given bad input where previously it
|
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would continue. Additionally, it can now continue when it encounters
|
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instructions which lack scheduling information. The behaviour can be
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controlled by the newly introduced
|
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``--skip-unsupported-instructions=<none|lack-sched|parse-failure|any>``, as
|
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documented in ``--help`` output and the command guide. (`#90474
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<https://github.com/llvm/llvm-project/pull/90474>`_)
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* llvm-readobj's LLVM output format for ELF core files has been changed.
|
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Similarly, the JSON format has been fixed for this case. The NT_FILE note
|
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now has a map for the mapped files. (`#92835
|
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<https://github.com/llvm/llvm-project/pull/92835>`_).
|
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* llvm-cov now generates HTML report with JavaScript code to allow simple
|
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jumping between uncovered parts (lines/regions/branches) of code
|
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using buttons on top-right corner of the page or using keys (L/R/B or
|
|
jumping in reverse direction with shift+L/R/B). (`#95662
|
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<https://github.com/llvm/llvm-project/pull/95662>`_).
|
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|
Changes to LLDB
|
|
---------------------------------
|
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|
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* Register field information is now provided on AArch64 FreeBSD for live
|
|
processes and core files (previously only provided on AArch64 Linux).
|
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* Register field information can now include enums to represent field
|
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values. Enums have been added for ``fpcr.RMode`` and ``mte_ctrl.TCF``
|
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for AArch64 targets::
|
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(lldb) register read fpcr
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fpcr = 0x00000000
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= (AHP = 0, DN = 0, FZ = 0, RMode = RN, <...>)
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If you need to know the values of the enum, these can be found in
|
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the output of ``register info`` for the same register.
|
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|
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Changes to BOLT
|
|
---------------------------------
|
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* Now supports ``--match-profile-with-function-hash`` to match profiled and
|
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binary functions with exact hash, allowing for the matching of renamed but
|
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identical functions.
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|
|
Changes to Sanitizers
|
|
---------------------
|
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|
|
Other Changes
|
|
-------------
|
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|
|
External Open Source Projects Using LLVM 19
|
|
===========================================
|
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|
|
* A project...
|
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|
|
Additional Information
|
|
======================
|
|
|
|
A wide variety of additional information is available on the `LLVM web page
|
|
<https://llvm.org/>`_, in particular in the `documentation
|
|
<https://llvm.org/docs/>`_ section. The web page also contains versions of the
|
|
API documentation which is up-to-date with the Git version of the source
|
|
code. You can access versions of these documents specific to this release by
|
|
going into the ``llvm/docs/`` directory in the LLVM tree.
|
|
|
|
If you have any questions or comments about LLVM, please feel free to contact
|
|
us via the `Discourse forums <https://discourse.llvm.org>`_.
|