Files
clang-p2996/llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir
Pushpinder Singh e2303a448e [FastRA] Fix handling of bundled MIs
Fast register allocator skips bundled MIs, as the main assignment
loop uses MachineBasicBlock::iterator (= MachineInstrBundleIterator)
This was causing SIInsertWaitcnts to crash which expects all
instructions to have registers assigned.

This patch makes sure to set everything inside bundle to the same
assignments done on BUNDLE header.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D90369
2020-12-21 02:10:55 -05:00

27 lines
993 B
YAML

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -run-pass=regallocfast %s -o - | FileCheck -check-prefixes=GCN,XNACK,GCX9 %s
---
name: fast_regalloc_bundle_handling
tracksRegLiveness: true
registers:
- { id: 0, class: vgpr_32 }
- { id: 1, class: vgpr_32 }
- { id: 2, class: vgpr_32 }
body: |
bb.0:
; GCN-LABEL: name: fast_regalloc_bundle_handling
; GCN: renamable $vgpr0 = IMPLICIT_DEF
; GCN: renamable $vgpr1 = IMPLICIT_DEF
; GCN: renamable $vgpr0 = BUNDLE implicit killed renamable $vgpr0, implicit killed renamable $vgpr1, implicit $exec {
; GCN: renamable $vgpr0 = V_ADD_U32_e32 $vgpr0, $vgpr1, implicit $exec
; GCN: }
; GCN: S_ENDPGM 0, implicit killed renamable $vgpr0
%0 = IMPLICIT_DEF
%1 = IMPLICIT_DEF
%2 = BUNDLE implicit %0, implicit %1, implicit $exec {
%2 = V_ADD_U32_e32 %0, %1, implicit $exec
}
S_ENDPGM 0, implicit %2
...