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clang-p2996/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
David Green b2ac9681a7 [ARM] Alter t2DoLoopStart to define lr 
This changes the definition of t2DoLoopStart from
t2DoLoopStart rGPR
to
GPRlr = t2DoLoopStart rGPR

This will hopefully mean that low overhead loops are more tied together,
and we can more reliably generate loops without reverting or being at
the whims of the register allocator.

This is a fairly simple change in itself, but leads to a number of other
required alterations.

 - The hardware loop pass, if UsePhi is set, now generates loops of the
   form:
       %start = llvm.start.loop.iterations(%N)
     loop:
       %p = phi [%start], [%dec]
       %dec = llvm.loop.decrement.reg(%p, 1)
       %c = icmp ne %dec, 0
       br %c, loop, exit
 - For this a new llvm.start.loop.iterations intrinsic was added, identical
   to llvm.set.loop.iterations but produces a value as seen above, gluing
   the loop together more through def-use chains.
 - This new instrinsic conceptually produces the same output as input,
   which is taught to SCEV so that the checks in MVETailPredication are not
   affected.
 - Some minor changes are needed to the ARMLowOverheadLoop pass, but it has
   been left mostly as before. We should now more reliably be able to tell
   that the t2DoLoopStart is correct without having to prove it, but
   t2WhileLoopStart and tail-predicated loops will remain the same.
 - And all the tests have been updated. There are a lot of them!

This patch on it's own might cause more trouble that it helps, with more
tail-predicated loops being reverted, but some additional patches can
hopefully improve upon that to get to something that is better overall.

Differential Revision: https://reviews.llvm.org/D89881
2020-11-10 15:57:58 +00:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
--- |
define dso_local arm_aapcscc void @test_debug(i32 %d, i32* %e, i16* nocapture readonly %k, i16* nocapture readonly %l) !dbg !15 {
entry:
call void @llvm.dbg.value(metadata i32 %d, metadata !23, metadata !DIExpression()), !dbg !32
call void @llvm.dbg.value(metadata i32* %e, metadata !24, metadata !DIExpression()), !dbg !32
call void @llvm.dbg.value(metadata i16* %k, metadata !25, metadata !DIExpression()), !dbg !32
call void @llvm.dbg.value(metadata i16* %l, metadata !26, metadata !DIExpression()), !dbg !32
call void @llvm.dbg.value(metadata i16 0, metadata !29, metadata !DIExpression()), !dbg !32
%call = tail call arm_aapcscc signext i16 @get_input(i32 %d, i32* %e, i16 signext 0) #4, !dbg !33
call void @llvm.dbg.value(metadata i16 %call, metadata !28, metadata !DIExpression()), !dbg !32
call void @llvm.dbg.value(metadata i32 0, metadata !30, metadata !DIExpression()), !dbg !32
%cmp30 = icmp sgt i32 %d, 0, !dbg !34
br i1 %cmp30, label %for.cond1.preheader.us.preheader, label %for.end11, !dbg !37
for.cond1.preheader.us.preheader: ; preds = %entry
%0 = shl i32 %d, 1, !dbg !37
br label %for.cond1.preheader.us, !dbg !37
for.cond1.preheader.us: ; preds = %for.cond1.preheader.us.preheader, %for.cond1.for.inc9_crit_edge.us
%lsr.iv2 = phi i16* [ %k, %for.cond1.preheader.us.preheader ], [ %9, %for.cond1.for.inc9_crit_edge.us ]
%i.031.us = phi i32 [ %inc10.us, %for.cond1.for.inc9_crit_edge.us ], [ 0, %for.cond1.preheader.us.preheader ]
call void @llvm.dbg.value(metadata i32 %i.031.us, metadata !30, metadata !DIExpression()), !dbg !32
call void @llvm.dbg.value(metadata i32 0, metadata !31, metadata !DIExpression()), !dbg !32
%arrayidx7.us = getelementptr inbounds i32, i32* %e, i32 %i.031.us, !dbg !38
%arrayidx7.promoted.us = load i32, i32* %arrayidx7.us, align 4, !dbg !41
%start = call i32 @llvm.start.loop.iterations.i32(i32 %d), !dbg !46
br label %for.body3.us, !dbg !46
for.body3.us: ; preds = %for.body3.us, %for.cond1.preheader.us
%lsr.iv5 = phi i16* [ %scevgep6, %for.body3.us ], [ %lsr.iv2, %for.cond1.preheader.us ], !dbg !32
%lsr.iv1 = phi i16* [ %scevgep, %for.body3.us ], [ %l, %for.cond1.preheader.us ], !dbg !32
%add829.us = phi i32 [ %arrayidx7.promoted.us, %for.cond1.preheader.us ], [ %add8.us, %for.body3.us ], !dbg !32
%1 = phi i32 [ %start, %for.cond1.preheader.us ], [ %4, %for.body3.us ], !dbg !32
call void @llvm.dbg.value(metadata i32 undef, metadata !31, metadata !DIExpression()), !dbg !32
%2 = load i16, i16* %lsr.iv5, align 2, !dbg !47
%conv.us = sext i16 %2 to i32, !dbg !47
%3 = load i16, i16* %lsr.iv1, align 2, !dbg !50
%conv5.us = sext i16 %3 to i32, !dbg !50
%mul6.us = mul nsw i32 %conv5.us, %conv.us, !dbg !51
%add8.us = add nsw i32 %mul6.us, %add829.us, !dbg !41
call void @llvm.dbg.value(metadata i32 undef, metadata !31, metadata !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value)), !dbg !32
%scevgep = getelementptr i16, i16* %lsr.iv1, i32 1, !dbg !52
%scevgep6 = getelementptr i16, i16* %lsr.iv5, i32 1, !dbg !52
%4 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1), !dbg !46
%5 = icmp ne i32 %4, 0, !dbg !46
br i1 %5, label %for.body3.us, label %for.cond1.for.inc9_crit_edge.us, !dbg !46, !llvm.loop !53
for.cond1.for.inc9_crit_edge.us: ; preds = %for.body3.us
%6 = bitcast i16* %lsr.iv2 to i1*
%sunkaddr = mul i32 %i.031.us, 4, !dbg !41
%7 = bitcast i32* %e to i8*, !dbg !41
%sunkaddr7 = getelementptr inbounds i8, i8* %7, i32 %sunkaddr, !dbg !41
%8 = bitcast i8* %sunkaddr7 to i32*, !dbg !41
store i32 %add8.us, i32* %8, align 4, !dbg !41
%inc10.us = add nuw nsw i32 %i.031.us, 1, !dbg !55
call void @llvm.dbg.value(metadata i32 %inc10.us, metadata !30, metadata !DIExpression()), !dbg !32
%scevgep4 = getelementptr i1, i1* %6, i32 %0, !dbg !37
%9 = bitcast i1* %scevgep4 to i16*, !dbg !37
%exitcond33 = icmp eq i32 %inc10.us, %d, !dbg !34
br i1 %exitcond33, label %for.end11, label %for.cond1.preheader.us, !dbg !37, !llvm.loop !56
for.end11: ; preds = %for.cond1.for.inc9_crit_edge.us, %entry
ret void, !dbg !58
}
declare !dbg !4 dso_local arm_aapcscc signext i16 @get_input(i32, i32*, i16 signext)
declare void @llvm.dbg.value(metadata, metadata, metadata)
declare i32 @llvm.start.loop.iterations.i32(i32)
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!10, !11, !12, !13}
!llvm.ident = !{!14}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 10.0.0 (https://github.com/llvm/llvm-project.git 9c91d79dadc660cb6a0ec736389341debd8cd118)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, splitDebugInlining: false, nameTableKind: None)
!1 = !DIFile(filename: "matrix-hang.c", directory: "/home/sampar01/src/tests/tail-predication")
!2 = !{}
!3 = !{!4}
!4 = !DISubprogram(name: "get_input", scope: !1, file: !1, line: 4, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
!5 = !DISubroutineType(types: !6)
!6 = !{!7, !8, !9, !7}
!7 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)
!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 32)
!10 = !{i32 7, !"Dwarf Version", i32 4}
!11 = !{i32 2, !"Debug Info Version", i32 3}
!12 = !{i32 1, !"wchar_size", i32 4}
!13 = !{i32 1, !"min_enum_size", i32 4}
!14 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git 9c91d79dadc660cb6a0ec736389341debd8cd118)"}
!15 = distinct !DISubprogram(name: "test_debug", scope: !1, file: !1, line: 6, type: !16, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !22)
!16 = !DISubroutineType(types: !17)
!17 = !{null, !18, !19, !21, !21}
!18 = !DIDerivedType(tag: DW_TAG_typedef, name: "a", file: !1, line: 1, baseType: !8)
!19 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !20, size: 32)
!20 = !DIDerivedType(tag: DW_TAG_typedef, name: "b", file: !1, line: 2, baseType: !8)
!21 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 32)
!22 = !{!23, !24, !25, !26, !27, !28, !29, !30, !31}
!23 = !DILocalVariable(name: "d", arg: 1, scope: !15, file: !1, line: 6, type: !18)
!24 = !DILocalVariable(name: "e", arg: 2, scope: !15, file: !1, line: 6, type: !19)
!25 = !DILocalVariable(name: "k", arg: 3, scope: !15, file: !1, line: 6, type: !21)
!26 = !DILocalVariable(name: "l", arg: 4, scope: !15, file: !1, line: 6, type: !21)
!27 = !DILocalVariable(name: "m", scope: !15, file: !1, line: 7, type: !7)
!28 = !DILocalVariable(name: "n", scope: !15, file: !1, line: 7, type: !7)
!29 = !DILocalVariable(name: "clipval", scope: !15, file: !1, line: 7, type: !7)
!30 = !DILocalVariable(name: "i", scope: !15, file: !1, line: 9, type: !18)
!31 = !DILocalVariable(name: "j", scope: !15, file: !1, line: 9, type: !18)
!32 = !DILocation(line: 0, scope: !15)
!33 = !DILocation(line: 8, column: 7, scope: !15)
!34 = !DILocation(line: 10, column: 17, scope: !35)
!35 = distinct !DILexicalBlock(scope: !36, file: !1, line: 10, column: 3)
!36 = distinct !DILexicalBlock(scope: !15, file: !1, line: 10, column: 3)
!37 = !DILocation(line: 10, column: 3, scope: !36)
!38 = !DILocation(line: 0, scope: !39)
!39 = distinct !DILexicalBlock(scope: !40, file: !1, line: 11, column: 5)
!40 = distinct !DILexicalBlock(scope: !35, file: !1, line: 11, column: 5)
!41 = !DILocation(line: 12, column: 12, scope: !39)
!42 = !{!43, !43, i64 0}
!43 = !{!"int", !44, i64 0}
!44 = !{!"omnipotent char", !45, i64 0}
!45 = !{!"Simple C/C++ TBAA"}
!46 = !DILocation(line: 11, column: 5, scope: !40)
!47 = !DILocation(line: 12, column: 15, scope: !39)
!48 = !{!49, !49, i64 0}
!49 = !{!"short", !44, i64 0}
!50 = !DILocation(line: 12, column: 30, scope: !39)
!51 = !DILocation(line: 12, column: 28, scope: !39)
!52 = !DILocation(line: 11, column: 19, scope: !39)
!53 = distinct !{!53, !46, !54}
!54 = !DILocation(line: 12, column: 33, scope: !40)
!55 = !DILocation(line: 10, column: 23, scope: !35)
!56 = distinct !{!56, !37, !57}
!57 = !DILocation(line: 12, column: 33, scope: !36)
!58 = !DILocation(line: 13, column: 1, scope: !15)
...
---
name: test_debug
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
- { reg: '$r3', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 32
offsetAdjustment: -24
maxAlignment: 4
adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test_debug
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.5(0x30000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
; CHECK: DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
; CHECK: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE $r5, $noreg, !25, !DIExpression(), debug-location !32
; CHECK: $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg, debug-location !33
; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE $r8, $noreg, !26, !DIExpression(), debug-location !32
; CHECK: $r9 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE $r9, $noreg, !24, !DIExpression(), debug-location !32
; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: DBG_VALUE 0, $noreg, !29, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $r10, $noreg, !23, !DIExpression(), debug-location !32
; CHECK: tBL 14 /* CC::al */, $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33
; CHECK: DBG_VALUE 0, $noreg, !30, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE $noreg, $noreg, !28, !DIExpression(), debug-location !32
; CHECK: t2CMPri renamable $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
; CHECK: tBcc %bb.5, 11 /* CC::lt */, killed $cpsr, debug-location !37
; CHECK: bb.1.for.cond1.preheader.us.preheader:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r5, $r8, $r9, $r10
; CHECK: renamable $r12 = t2LSLri renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg, debug-location !37
; CHECK: renamable $r1, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.cond1.preheader.us:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: liveins: $r1, $r5, $r8, $r9, $r10, $r12
; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
; CHECK: DBG_VALUE 0, $noreg, !31, !DIExpression(), debug-location !32
; CHECK: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (load 4 from %ir.arrayidx7.us)
; CHECK: $r3 = tMOVr $r5, 14 /* CC::al */, $noreg, debug-location !32
; CHECK: $r0 = tMOVr $r8, 14 /* CC::al */, $noreg, debug-location !32
; CHECK: $lr = t2DLS renamable $r10, debug-location !42
; CHECK: bb.3.for.body3.us:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r8, $r9, $r10, $r12
; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(), debug-location !32
; CHECK: renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !43 :: (load 2 from %ir.lsr.iv5)
; CHECK: renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14 /* CC::al */, $noreg, debug-location !44 :: (load 2 from %ir.lsr.iv1)
; CHECK: renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14 /* CC::al */, $noreg, debug-location !41
; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !32
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3, debug-location !42
; CHECK: bb.4.for.cond1.for.inc9_crit_edge.us:
; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $r1, $r2, $r5, $r8, $r9, $r10, $r12
; CHECK: t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14 /* CC::al */, $noreg, debug-location !41 :: (store 4 into %ir.8)
; CHECK: renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14 /* CC::al */, $noreg, debug-location !49
; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14 /* CC::al */, $noreg, debug-location !37
; CHECK: tCMPhir renamable $r1, renamable $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !37
; CHECK: tBcc %bb.2, 1 /* CC::ne */, killed $cpsr, debug-location !37
; CHECK: bb.5.for.end11:
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10, debug-location !52
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !52
bb.0.entry:
successors: %bb.1(0x50000000), %bb.5(0x30000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
DBG_VALUE $r0, $noreg, !23, !DIExpression(), debug-location !32
DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32
DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32
DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 20
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8
frame-setup CFI_INSTRUCTION offset $r6, -12
frame-setup CFI_INSTRUCTION offset $r5, -16
frame-setup CFI_INSTRUCTION offset $r4, -20
$r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa $r7, 8
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10
frame-setup CFI_INSTRUCTION offset $r10, -24
frame-setup CFI_INSTRUCTION offset $r9, -28
frame-setup CFI_INSTRUCTION offset $r8, -32
$r5 = tMOVr killed $r2, 14, $noreg
DBG_VALUE $r5, $noreg, !25, !DIExpression(), debug-location !32
$r2, dead $cpsr = tMOVi8 0, 14, $noreg, debug-location !33
$r8 = tMOVr killed $r3, 14, $noreg
DBG_VALUE $r8, $noreg, !26, !DIExpression(), debug-location !32
$r9 = tMOVr $r1, 14, $noreg
DBG_VALUE $r9, $noreg, !24, !DIExpression(), debug-location !32
$r10 = tMOVr $r0, 14, $noreg
DBG_VALUE 0, $noreg, !29, !DIExpression(), debug-location !32
DBG_VALUE $r10, $noreg, !23, !DIExpression(), debug-location !32
tBL 14, $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33
DBG_VALUE 0, $noreg, !30, !DIExpression(), debug-location !32
DBG_VALUE $noreg, $noreg, !28, !DIExpression(), debug-location !32
t2CMPri renamable $r10, 1, 14, $noreg, implicit-def $cpsr, debug-location !37
tBcc %bb.5, 11, killed $cpsr, debug-location !37
bb.1.for.cond1.preheader.us.preheader:
successors: %bb.2(0x80000000)
liveins: $r5, $r8, $r9, $r10
renamable $r12 = t2LSLri renamable $r10, 1, 14, $noreg, $noreg, debug-location !37
renamable $r1, dead $cpsr = tMOVi8 0, 14, $noreg
bb.2.for.cond1.preheader.us:
successors: %bb.3(0x80000000)
liveins: $r1, $r5, $r8, $r9, $r10, $r12
DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
DBG_VALUE 0, $noreg, !31, !DIExpression(), debug-location !32
renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14, $noreg, debug-location !41 :: (load 4 from %ir.arrayidx7.us)
$r3 = tMOVr $r5, 14, $noreg, debug-location !32
$r0 = tMOVr $r8, 14, $noreg, debug-location !32
$lr = tMOVr $r10, 14, $noreg, debug-location !32
$lr = t2DoLoopStart renamable $r10, debug-location !46
bb.3.for.body3.us:
successors: %bb.3(0x7c000000), %bb.4(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r8, $r9, $r10, $r12
DBG_VALUE $noreg, $noreg, !31, !DIExpression(), debug-location !32
renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14, $noreg, debug-location !47 :: (load 2 from %ir.lsr.iv5)
renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !46
renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14, $noreg, debug-location !50 :: (load 2 from %ir.lsr.iv1)
renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14, $noreg, debug-location !41
DBG_VALUE $noreg, $noreg, !31, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !32
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr, debug-location !46
tB %bb.4, 14, $noreg, debug-location !46
bb.4.for.cond1.for.inc9_crit_edge.us:
successors: %bb.5(0x04000000), %bb.2(0x7c000000)
liveins: $r1, $r2, $r5, $r8, $r9, $r10, $r12
t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14, $noreg, debug-location !41 :: (store 4 into %ir.8)
renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14, $noreg, debug-location !55
DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32
renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14, $noreg, debug-location !37
tCMPhir renamable $r1, renamable $r10, 14, $noreg, implicit-def $cpsr, debug-location !37
tBcc %bb.2, 1, killed $cpsr, debug-location !37
bb.5.for.end11:
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10, debug-location !58
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !58
...
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