Michael Maitland 594b92a7b9 [RISCV] Add Tune to DontSinkSplatOperands (#79199) ...

A CPU may prefer to not sink splat operands, one reason being that it
could require a S2V transfer buffer to move scalars into buffers.

2024-01-25 14:44:36 -05:00

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AArch64

[AArch64] Combine store (trunc X to <3 x i8>) to sequence of ST1.b. (#78637)

2024-01-25 18:28:44 +00:00

AMDGPU

[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX11.5 (#79460)

2024-01-25 16:28:49 +00:00

ARC

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ARM

[Thumb,ELF] Fix access to dso_preemptable __stack_chk_guard with static relocation model (#78950)

2024-01-22 13:16:31 -08:00

AVR

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BPF

[InstCombine] Canonicalize constant GEPs to i8 source element type (#68882)

2024-01-24 15:25:29 +01:00

CSKY

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DirectX

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Generic

[AsmPrinter] Remove mbb-profile-dump flag (#76595)

2024-01-23 16:48:10 -08:00

Hexagon

[HEXAGON] Inlining Division (#79021)

2024-01-24 09:30:33 -06:00

Inputs

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Lanai

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LoongArch

[CodeGen][LoongArch] Set FP_TO_SINT/FP_TO_UINT to legal for vector types (#79107)

2024-01-23 15:57:06 +08:00

M68k

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Mips

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MIR

[AMDGPU] Add mark last scratch load pass (#75512)

2024-01-18 09:36:44 +01:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] use incomplete aggregate initializers (#79062)

2024-01-24 09:24:28 -08:00

PowerPC

Require asserts for llvm/test/CodeGen/PowerPC/sms-regpress.mir.

2024-01-22 13:51:03 -08:00

RISCV

[RISCV] Add Tune to DontSinkSplatOperands (#79199)

2024-01-25 14:44:36 -05:00

SPARC

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SPIRV

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SystemZ

[SystemZ] Require D12 for i128 accesses in isLegalAddressingMode() (#79221)

2024-01-24 20:16:05 +01:00

Thumb

[test] Update stack_guard_remat.ll (#79139)

2024-01-23 14:48:33 +01:00

Thumb2

[ARM] Fix MVEFloatOps check on creating VCVTN (#79291)

2024-01-25 08:12:51 +00:00

VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

Revert "[X86] Fold not(pcmpeq(and(X,CstPow2),0)) -> pcmpeq(and(X,CstPow2),CstPow2)"

2024-01-25 09:40:16 -08:00

XCore

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