578741b5e8
Currently, we use `AAAMDWavesPerEU` to iteratively update values based on attributes from the associated function, potentially propagating user-annotated values, along with `AAAMDFlatWorkGroupSize`. Similarly, we have `AAAMDFlatWorkGroupSize`. However, since the value calculated through the flat workgroup size always dominates the user annotation (i.e., the attribute), running `AAAMDWavesPerEU` iteratively is unnecessary if no user-annotated value exists. This PR completely rewrites how the `amdgpu-waves-per-eu` attribute is handled in `AMDGPUAttributor`. The key changes are as follows: - `AAAMDFlatWorkGroupSize` remains unchanged. - `AAAMDWavesPerEU` now only propagates user-annotated values. - A new function is added to check and update `amdgpu-waves-per-eu` based on the following rules: - No waves per eu, no flat workgroup size: Assume a flat workgroup size of `1,1024` and compute waves per eu based on this. - No waves per eu, flat workgroup size exists: Use the provided flat workgroup size to compute waves-per-eu. - Waves per eu exists, no flat workgroup size: This is a tricky case. In this PR, we assume a flat workgroup size of `1,1024`, but this can be adjusted if a different approach is preferred. Alternatively, we could directly use the user-annotated value. - Both waves per eu and flat workgroup size exist: If there’s a conflict, the value derived from the flat workgroup size takes precedence over waves per eu. This PR also updates the logic for merging two waves per eu pairs. The current implementation, which uses `clampStateAndIndicateChange` to compute a union, might not be ideal. If we think from ensure proper resource allocation perspective, for instance, if one pair specifies a minimum of 2 waves per eu, and another specifies a minimum of 4, we should guarantee that 4 waves per eu can be supported, as failing to do so could result in excessive resource allocation per wave. A similar principle applies to the upper bound. Thus, the PR uses the following approach for merging two pairs, `lo_a,up_a` and `lo_b,up_b`: `max(lo_a, lo_b), max(up_a, up_b)`. This ensures that resource allocation adheres to the stricter constraints from both inputs. Fix #123092.
69 lines
3.5 KiB
LLVM
69 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck -check-prefix=ATTRIBUTOR_GCN %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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define internal void @indirect() {
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; ATTRIBUTOR_GCN-LABEL: define {{[^@]+}}@indirect
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; ATTRIBUTOR_GCN-SAME: () #[[ATTR0:[0-9]+]] {
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; ATTRIBUTOR_GCN-NEXT: ret void
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;
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; GFX9-LABEL: indirect:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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ret void
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}
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define amdgpu_kernel void @test_simple_indirect_call() {
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; ATTRIBUTOR_GCN-LABEL: define {{[^@]+}}@test_simple_indirect_call
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; ATTRIBUTOR_GCN-SAME: () #[[ATTR1:[0-9]+]] {
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; ATTRIBUTOR_GCN-NEXT: [[FPTR:%.*]] = alloca ptr, align 8, addrspace(5)
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; ATTRIBUTOR_GCN-NEXT: store ptr @indirect, ptr addrspace(5) [[FPTR]], align 8
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; ATTRIBUTOR_GCN-NEXT: [[FP:%.*]] = load ptr, ptr addrspace(5) [[FPTR]], align 8
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; ATTRIBUTOR_GCN-NEXT: call void @indirect()
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; ATTRIBUTOR_GCN-NEXT: ret void
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;
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; GFX9-LABEL: test_simple_indirect_call:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GFX9-NEXT: s_mov_b32 s13, s15
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; GFX9-NEXT: s_mov_b32 s12, s14
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; GFX9-NEXT: s_load_dwordx2 s[14:15], s[4:5], 0x4
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; GFX9-NEXT: s_add_u32 s0, s0, s17
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; GFX9-NEXT: s_addc_u32 s1, s1, 0
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; GFX9-NEXT: s_mov_b32 s32, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_lshr_b32 s14, s14, 16
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; GFX9-NEXT: s_mul_i32 s14, s14, s15
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; GFX9-NEXT: v_mul_lo_u32 v3, s14, v0
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; GFX9-NEXT: s_getpc_b64 s[18:19]
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; GFX9-NEXT: s_add_u32 s18, s18, indirect@rel32@lo+4
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; GFX9-NEXT: s_addc_u32 s19, s19, indirect@rel32@hi+12
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; GFX9-NEXT: s_mov_b32 s14, s16
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; GFX9-NEXT: v_mad_u32_u24 v3, v1, s15, v3
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; GFX9-NEXT: v_add_lshl_u32 v5, v3, v2, 3
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; GFX9-NEXT: v_mov_b32_e32 v3, s18
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; GFX9-NEXT: v_lshlrev_b32_e32 v2, 20, v2
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; GFX9-NEXT: v_lshlrev_b32_e32 v1, 10, v1
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; GFX9-NEXT: v_mov_b32_e32 v4, s19
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; GFX9-NEXT: v_or3_b32 v31, v0, v1, v2
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; GFX9-NEXT: ds_write_b64 v5, v[3:4]
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; GFX9-NEXT: s_swappc_b64 s[30:31], s[18:19]
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; GFX9-NEXT: s_endpgm
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%fptr = alloca ptr, addrspace(5)
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%fptr.cast = addrspacecast ptr addrspace(5) %fptr to ptr
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store ptr @indirect, ptr %fptr.cast
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%fp = load ptr, ptr %fptr.cast
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call void %fp()
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ret void
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}
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;.
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;.
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; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; ATTRIBUTOR_GCN: attributes #[[ATTR1]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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;.
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