bb03cdcb44
Follow-up to #140494 `shouldForceRelocation` is conservative and produces redundant relocations. For example, RISCVAsmBackend::ForceRelocs (introduced to support mixed relax/norelax code) leads to redundant relocations in the following example adapted from #77436 ``` .option norelax j label // For assembly input, RISCVAsmParser::ParseInstruction sets ForceRelocs (https://reviews.llvm.org/D46423). // For direct object emission, RISCVELFStreamer sets ForceRelocs (#77436) .option relax call foo // linker-relaxable .option norelax j label // redundant relocation due to ForceRelocs .option relax label: ``` Root problem: The `isSymbolRefDifferenceFullyResolvedImpl` condition in MCAssembler::evaluateFixup does not check whether two locations are separated by a fragment whose size can be indeterminate due to linker instruction (e.g. MCDataFragment with relaxation, or MCAlignFragment due to indeterminate start offst). This patch * Updates the fragment walk code in `attemptToFoldSymbolOffsetDifference` to treat MCRelaxableFragment (for --riscv-asm-relax-branches) as fixed size after finishLayout. * Adds a condition in `addReloc` to complement `isSymbolRefDifferenceFullyResolvedImpl`. * Removes the no longer needed `shouldForceRelocation`. This fragment walk code path handles nicely handles mixed relax/norelax case from https://discourse.llvm.org/t/possible-problem-related-to-subtarget-usage/75283 and allows us to remove `MCSubtargetInfo` argument (#73721) as a follow-up. This fragment walk code should be avoided in the absence of linker-relaxable fragments within the current section. Adjust two bolt/test/RISCV tests (#141310) Pull Request: https://github.com/llvm/llvm-project/pull/140692
35 lines
796 B
ArmAsm
35 lines
796 B
ArmAsm
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
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# RUN: | llvm-objdump -M no-aliases -dr - \
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# RUN: | FileCheck -check-prefix=CHECK-INSTR %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
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.LBB0:
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.LBB1:
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## This is linker-relaxable to avoid resolving the following fixups
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call relax
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jal zero, .LBB0+16
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# CHECK-INSTR: jal zero, 0x10
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# CHECK-RELOC: R_RISCV_JAL
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beq a0, a1, .LBB1+32
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# CHECK-INSTR: beq a0, a1, 0x20
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# CHECK-RELOC-NEXT: R_RISCV_BRANCH
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c.j .+32
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# CHECK-INSTR: c.j 0x30
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c.j .LBB2+4
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# CHECK-INSTR: c.j 0x22
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# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP
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c.beqz a0, .-2
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# CHECK-INSTR: c.beqz a0, 0x12
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call relax
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# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT
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.LBB2:
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