82812fb986
Implement and test replace_lane instructions. Patch by Thomas Lively Differential Revision: https://reviews.llvm.org/D50750 llvm-svn: 339786
290 lines
10 KiB
LLVM
290 lines
10 KiB
LLVM
; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128,+sign-ext --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that basic SIMD128 vector manipulation operations assemble as expected.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; ==============================================================================
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; 16 x i8
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; ==============================================================================
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; CHECK-LABEL: splat_v16i8:
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.splat $push0=, $0 # encoding: [0xfd,0x03]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <16 x i8> @splat_v16i8(i8 %x) {
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%v = insertelement <16 x i8> undef, i8 %x, i32 0
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%res = shufflevector <16 x i8> %v, <16 x i8> undef,
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<16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
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i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: extract_v16i8_s:
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i8x16.extract_lane_s $push0=, $0, 13 # encoding: [0xfd,0x09,0x0d]{{$}}
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; SIMD128: return $pop0 #
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define i32 @extract_v16i8_s(<16 x i8> %v) {
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%elem = extractelement <16 x i8> %v, i8 13
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%a = sext i8 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v16i8_u:
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
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; SIMD128: return $pop0 #
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define i32 @extract_v16i8_u(<16 x i8> %v) {
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%elem = extractelement <16 x i8> %v, i8 13
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%a = zext i8 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v16i8:
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i8x16.extract_lane_u $push0=, $0, 13 # encoding: [0xfd,0x0a,0x0d]{{$}}
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; SIMD128: return $pop0 #
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define i8 @extract_v16i8(<16 x i8> %v) {
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%elem = extractelement <16 x i8> %v, i8 13
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ret i8 %elem
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}
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; CHECK-LABEL: replace_v16i8:
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.replace_lane $push0=, $0, 11, $1 # encoding: [0xfd,0x11,0x0b]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <16 x i8> @replace_v16i8(<16 x i8> %v, i8 %x) {
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%res = insertelement <16 x i8> %v, i8 %x, i32 11
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ret <16 x i8> %res
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}
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; ==============================================================================
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; 8 x i16
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; ==============================================================================
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; CHECK-LABEL: splat_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.splat $push0=, $0 # encoding: [0xfd,0x04]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <8 x i16> @splat_v8i16(i16 %x) {
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%v = insertelement <8 x i16> undef, i16 %x, i32 0
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%res = shufflevector <8 x i16> %v, <8 x i16> undef,
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<8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: extract_v8i16_s:
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i16x8.extract_lane_s $push0=, $0, 5 # encoding: [0xfd,0x0b,0x05]{{$}}
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; SIMD128: return $pop0 #
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define i32 @extract_v8i16_s(<8 x i16> %v) {
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%elem = extractelement <8 x i16> %v, i16 5
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%a = sext i16 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v8i16_u:
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
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; SIMD128: return $pop0 #
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define i32 @extract_v8i16_u(<8 x i16> %v) {
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%elem = extractelement <8 x i16> %v, i16 5
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%a = zext i16 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i16x8.extract_lane_u $push0=, $0, 5 # encoding: [0xfd,0x0c,0x05]{{$}}
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; SIMD128: return $pop0 #
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define i16 @extract_v8i16(<8 x i16> %v) {
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%elem = extractelement <8 x i16> %v, i16 5
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ret i16 %elem
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}
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; CHECK-LABEL: replace_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.replace_lane $push0=, $0, 7, $1 # encoding: [0xfd,0x12,0x07]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <8 x i16> @replace_v8i16(<8 x i16> %v, i16 %x) {
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%res = insertelement <8 x i16> %v, i16 %x, i32 7
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ret <8 x i16> %res
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}
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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; CHECK-LABEL: splat_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.splat $push0=, $0 # encoding: [0xfd,0x05]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <4 x i32> @splat_v4i32(i32 %x) {
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%v = insertelement <4 x i32> undef, i32 %x, i32 0
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%res = shufflevector <4 x i32> %v, <4 x i32> undef,
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<4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: extract_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0d,0x03]{{$}}
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; SIMD128: return $pop0 #
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define i32 @extract_v4i32(<4 x i32> %v) {
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%elem = extractelement <4 x i32> %v, i32 3
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ret i32 %elem
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}
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; CHECK-LABEL: replace_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.replace_lane $push0=, $0, 2, $1 # encoding: [0xfd,0x13,0x02]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <4 x i32> @replace_v4i32(<4 x i32> %v, i32 %x) {
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%res = insertelement <4 x i32> %v, i32 %x, i32 2
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ret <4 x i32> %res
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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; CHECK-LABEL: splat_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param i64{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.splat $push0=, $0 # encoding: [0xfd,0x06]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <2 x i64> @splat_v2i64(i64 %x) {
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%t1 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
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%res = insertelement <2 x i64> %t1, i64 %x, i32 1
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ret <2 x i64> %res
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}
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; CHECK-LABEL: extract_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i64{{$}}
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; SIMD128: i64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x0e,0x01]{{$}}
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; SIMD128: return $pop0 #
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define i64 @extract_v2i64(<2 x i64> %v) {
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%elem = extractelement <2 x i64> %v, i64 1
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ret i64 %elem
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}
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; CHECK-LABEL: replace_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, i64{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.replace_lane $push0=, $0, 0, $1 # encoding: [0xfd,0x14,0x00]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <2 x i64> @replace_v2i64(<2 x i64> %v, i64 %x) {
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%res = insertelement <2 x i64> %v, i64 %x, i32 0
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ret <2 x i64> %res
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}
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; ==============================================================================
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; 4 x f32
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; ==============================================================================
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; CHECK-LABEL: splat_v4f32:
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param f32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.splat $push0=, $0 # encoding: [0xfd,0x07]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <4 x float> @splat_v4f32(float %x) {
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%v = insertelement <4 x float> undef, float %x, i32 0
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%res = shufflevector <4 x float> %v, <4 x float> undef,
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<4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x float> %res
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}
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; CHECK-LABEL: extract_v4f32:
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128{{$}}
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; SIMD128: .result f32{{$}}
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; SIMD128: f32x4.extract_lane $push0=, $0, 3 # encoding: [0xfd,0x0f,0x03]{{$}}
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; SIMD128: return $pop0 #
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define float @extract_v4f32(<4 x float> %v) {
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%elem = extractelement <4 x float> %v, i32 3
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ret float %elem
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}
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; CHECK-LABEL: replace_v4f32:
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, f32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.replace_lane $push0=, $0, 2, $1 # encoding: [0xfd,0x15,0x02]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <4 x float> @replace_v4f32(<4 x float> %v, float %x) {
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%res = insertelement <4 x float> %v, float %x, i32 2
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ret <4 x float> %res
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}
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; ==============================================================================
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; 2 x f64
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; ==============================================================================
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; CHECK-LABEL: splat_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-VM-NOT: f64x2
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; SIMD128: .param f64{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.splat $push0=, $0 # encoding: [0xfd,0x08]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <2 x double> @splat_v2f64(double %x) {
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%t1 = insertelement <2 x double> zeroinitializer, double %x, i3 0
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%res = insertelement <2 x double> %t1, double %x, i32 1
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ret <2 x double> %res
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}
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; CHECK-LABEL: extract_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-VM-NOT: f64x2
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; SIMD128: .param v128{{$}}
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; SIMD128: .result f64{{$}}
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; SIMD128: f64x2.extract_lane $push0=, $0, 1 # encoding: [0xfd,0x10,0x01]{{$}}
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; SIMD128: return $pop0 #
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define double @extract_v2f64(<2 x double> %v) {
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%elem = extractelement <2 x double> %v, i32 1
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ret double %elem
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}
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; CHECK-LABEL: replace_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-VM-NOT: f64x2
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; SIMD128: .param v128, f64{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.replace_lane $push0=, $0, 0, $1 # encoding: [0xfd,0x16,0x00]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <2 x double> @replace_v2f64(<2 x double> %v, double %x) {
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%res = insertelement <2 x double> %v, double %x, i32 0
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ret <2 x double> %res
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}
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