bb83a3df25
This introduces the new `--print-enabled-extensions` command line option to AArch64, which prints the list of extensions that are enabled for the target specified by the combination of `--target`/`-march`/`-mcpu` values. The goal of the this option is both to enable the manual inspection of the enabled extensions by users and to enhance the testability of architecture versions and CPU targets implemented in the compiler. As part of this change, a new field for `FEAT_*` architecture feature names was added to the TableGen entries. The output of the existing `--print-supported-extensions` option was updated accordingly to show these in a separate column.
340 lines
10 KiB
C++
340 lines
10 KiB
C++
//===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise AArch64 hardware features
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// such as FPU/CPU/ARCH and extension names.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/TargetParser/AArch64TargetParser.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/ARMTargetParserCommon.h"
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#include "llvm/TargetParser/Triple.h"
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#include <cctype>
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#include <vector>
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#define DEBUG_TYPE "target-parser"
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using namespace llvm;
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#define EMIT_FMV_INFO
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#include "llvm/TargetParser/AArch64TargetParserDef.inc"
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static unsigned checkArchVersion(llvm::StringRef Arch) {
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if (Arch.size() >= 2 && Arch[0] == 'v' && std::isdigit(Arch[1]))
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return (Arch[1] - 48);
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return 0;
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}
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const AArch64::ArchInfo *AArch64::getArchForCpu(StringRef CPU) {
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// Note: this now takes cpu aliases into account
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std::optional<CpuInfo> Cpu = parseCpu(CPU);
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if (!Cpu)
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return nullptr;
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return &Cpu->Arch;
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}
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std::optional<AArch64::ArchInfo> AArch64::ArchInfo::findBySubArch(StringRef SubArch) {
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for (const auto *A : AArch64::ArchInfos)
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if (A->getSubArch() == SubArch)
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return *A;
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return {};
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}
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uint64_t AArch64::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
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uint64_t FeaturesMask = 0;
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for (const StringRef &FeatureStr : FeatureStrs) {
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if (auto Ext = parseFMVExtension(FeatureStr))
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FeaturesMask |= (1ULL << Ext->Bit);
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}
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return FeaturesMask;
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}
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bool AArch64::getExtensionFeatures(
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const AArch64::ExtensionBitset &InputExts,
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std::vector<StringRef> &Features) {
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for (const auto &E : Extensions)
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/* INVALID and NONE have no feature name. */
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if (InputExts.test(E.ID) && !E.PosTargetFeature.empty())
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Features.push_back(E.PosTargetFeature);
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return true;
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}
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StringRef AArch64::resolveCPUAlias(StringRef Name) {
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for (const auto &A : CpuAliases)
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if (A.AltName == Name)
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return A.Name;
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return Name;
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}
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StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
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bool IsNegated = ArchExt.starts_with("no");
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StringRef ArchExtBase = IsNegated ? ArchExt.drop_front(2) : ArchExt;
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if (auto AE = parseArchExtension(ArchExtBase)) {
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assert(!(AE.has_value() && AE->NegTargetFeature.empty()));
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return IsNegated ? AE->NegTargetFeature : AE->PosTargetFeature;
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}
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return StringRef();
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}
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void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
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for (const auto &C : CpuInfos)
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Values.push_back(C.Name);
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for (const auto &Alias : CpuAliases)
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Values.push_back(Alias.AltName);
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}
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bool AArch64::isX18ReservedByDefault(const Triple &TT) {
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return TT.isAndroid() || TT.isOSDarwin() || TT.isOSFuchsia() ||
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TT.isOSWindows() || TT.isOHOSFamily();
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}
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// Allows partial match, ex. "v8a" matches "armv8a".
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const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) {
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Arch = llvm::ARM::getCanonicalArchName(Arch);
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if (checkArchVersion(Arch) < 8)
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return {};
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StringRef Syn = llvm::ARM::getArchSynonym(Arch);
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for (const auto *A : ArchInfos) {
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if (A->Name.ends_with(Syn))
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return A;
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}
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return {};
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}
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std::optional<AArch64::ExtensionInfo>
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AArch64::parseArchExtension(StringRef ArchExt) {
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if (ArchExt.empty())
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return {};
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for (const auto &A : Extensions) {
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if (ArchExt == A.UserVisibleName || ArchExt == A.Alias)
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return A;
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}
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return {};
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}
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std::optional<AArch64::FMVInfo> AArch64::parseFMVExtension(StringRef FMVExt) {
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// FIXME introduce general alias functionality, or remove this exception.
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if (FMVExt == "rdma")
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FMVExt = "rdm";
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for (const auto &I : getFMVInfo()) {
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if (FMVExt == I.Name)
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return I;
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}
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return {};
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}
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std::optional<AArch64::ExtensionInfo>
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AArch64::targetFeatureToExtension(StringRef TargetFeature) {
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for (const auto &E : Extensions)
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if (TargetFeature == E.PosTargetFeature)
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return E;
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return {};
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}
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std::optional<AArch64::CpuInfo> AArch64::parseCpu(StringRef Name) {
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// Resolve aliases first.
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Name = resolveCPUAlias(Name);
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// Then find the CPU name.
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for (const auto &C : CpuInfos)
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if (Name == C.Name)
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return C;
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return {};
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}
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void AArch64::PrintSupportedExtensions() {
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outs() << "All available -march extensions for AArch64\n\n"
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<< " " << left_justify("Name", 20)
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<< left_justify("Architecture Feature(s)", 55)
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<< "Description\n";
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for (const auto &Ext : Extensions) {
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// Extensions without a feature cannot be used with -march.
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if (!Ext.UserVisibleName.empty() && !Ext.PosTargetFeature.empty()) {
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outs() << " "
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<< format(Ext.Description.empty() ? "%-20s%s\n" : "%-20s%-55s%s\n",
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Ext.UserVisibleName.str().c_str(),
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Ext.ArchFeatureName.str().c_str(),
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Ext.Description.str().c_str());
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}
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}
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}
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void
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AArch64::printEnabledExtensions(const std::set<StringRef> &EnabledFeatureNames) {
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outs() << "Extensions enabled for the given AArch64 target\n\n"
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<< " " << left_justify("Architecture Feature(s)", 55)
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<< "Description\n";
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std::vector<ExtensionInfo> EnabledExtensionsInfo;
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for (const auto &FeatureName : EnabledFeatureNames) {
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std::string PosFeatureName = '+' + FeatureName.str();
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if (auto ExtInfo = targetFeatureToExtension(PosFeatureName))
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EnabledExtensionsInfo.push_back(*ExtInfo);
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}
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std::sort(EnabledExtensionsInfo.begin(), EnabledExtensionsInfo.end(),
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[](const ExtensionInfo &Lhs, const ExtensionInfo &Rhs) {
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return Lhs.ArchFeatureName < Rhs.ArchFeatureName;
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});
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for (const auto &Ext : EnabledExtensionsInfo) {
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outs() << " "
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<< format("%-55s%s\n",
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Ext.ArchFeatureName.str().c_str(),
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Ext.Description.str().c_str());
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}
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}
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const llvm::AArch64::ExtensionInfo &
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lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
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for (const auto &E : llvm::AArch64::Extensions)
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if (E.ID == ExtID)
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return E;
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llvm_unreachable("Invalid extension ID");
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}
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void AArch64::ExtensionSet::enable(ArchExtKind E) {
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if (Enabled.test(E))
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return;
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LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).UserVisibleName << "\n");
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Touched.set(E);
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Enabled.set(E);
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// Recursively enable all features that this one depends on. This handles all
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// of the simple cases, where the behaviour doesn't depend on the base
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// architecture version.
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for (auto Dep : ExtensionDependencies)
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if (E == Dep.Later)
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enable(Dep.Earlier);
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// Special cases for dependencies which vary depending on the base
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// architecture version.
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if (BaseArch) {
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// +fp16 implies +fp16fml for v8.4A+, but not v9.0-A+
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if (E == AEK_FP16 && BaseArch->is_superset(ARMV8_4A) &&
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!BaseArch->is_superset(ARMV9A))
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enable(AEK_FP16FML);
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// For v8.4A+ and v9.0A+, +crypto also enables +sha3 and +sm4.
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if (E == AEK_CRYPTO && BaseArch->is_superset(ARMV8_4A)) {
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enable(AEK_SHA3);
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enable(AEK_SM4);
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}
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}
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}
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void AArch64::ExtensionSet::disable(ArchExtKind E) {
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// -crypto always disables aes, sha2, sha3 and sm4, even for architectures
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// where the latter two would not be enabled by +crypto.
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if (E == AEK_CRYPTO) {
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disable(AEK_AES);
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disable(AEK_SHA2);
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disable(AEK_SHA3);
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disable(AEK_SM4);
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}
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if (!Enabled.test(E))
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return;
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LLVM_DEBUG(llvm::dbgs() << "Disable " << lookupExtensionByID(E).UserVisibleName << "\n");
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Touched.set(E);
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Enabled.reset(E);
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// Recursively disable all features that depends on this one.
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for (auto Dep : ExtensionDependencies)
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if (E == Dep.Earlier)
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disable(Dep.Later);
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}
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void AArch64::ExtensionSet::addCPUDefaults(const CpuInfo &CPU) {
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LLVM_DEBUG(llvm::dbgs() << "addCPUDefaults(" << CPU.Name << ")\n");
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BaseArch = &CPU.Arch;
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AArch64::ExtensionBitset CPUExtensions = CPU.getImpliedExtensions();
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for (const auto &E : Extensions)
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if (CPUExtensions.test(E.ID))
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enable(E.ID);
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}
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void AArch64::ExtensionSet::addArchDefaults(const ArchInfo &Arch) {
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LLVM_DEBUG(llvm::dbgs() << "addArchDefaults(" << Arch.Name << ")\n");
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BaseArch = &Arch;
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for (const auto &E : Extensions)
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if (Arch.DefaultExts.test(E.ID))
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enable(E.ID);
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}
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bool AArch64::ExtensionSet::parseModifier(StringRef Modifier,
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const bool AllowNoDashForm) {
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LLVM_DEBUG(llvm::dbgs() << "parseModifier(" << Modifier << ")\n");
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size_t NChars = 0;
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// The "no-feat" form is allowed in the target attribute but nowhere else.
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if (AllowNoDashForm && Modifier.starts_with("no-"))
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NChars = 3;
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else if (Modifier.starts_with("no"))
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NChars = 2;
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bool IsNegated = NChars != 0;
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StringRef ArchExt = Modifier.drop_front(NChars);
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if (auto AE = parseArchExtension(ArchExt)) {
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if (AE->PosTargetFeature.empty() || AE->NegTargetFeature.empty())
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return false;
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if (IsNegated)
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disable(AE->ID);
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else
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enable(AE->ID);
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return true;
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}
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return false;
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}
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void AArch64::ExtensionSet::reconstructFromParsedFeatures(
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const std::vector<std::string> &Features,
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std::vector<std::string> &NonExtensions) {
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assert(Touched.none() && "Bitset already initialized");
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for (auto &F : Features) {
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bool IsNegated = F[0] == '-';
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if (auto AE = targetFeatureToExtension(F)) {
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Touched.set(AE->ID);
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if (IsNegated)
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Enabled.reset(AE->ID);
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else
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Enabled.set(AE->ID);
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continue;
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}
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NonExtensions.push_back(F);
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}
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}
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void AArch64::ExtensionSet::dump() const {
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std::vector<StringRef> Features;
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toLLVMFeatureList(Features);
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for (StringRef F : Features)
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llvm::outs() << F << " ";
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llvm::outs() << "\n";
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}
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const AArch64::ExtensionInfo &
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AArch64::getExtensionByID(AArch64::ArchExtKind ExtID) {
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return lookupExtensionByID(ExtID);
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}
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