e99d8bb0dc
LBARX loads a byte from memory into a register, automatically setting
the remaining bits of the register to zero. If a subsequent RLWINM
instruction is used to clear those same bits (which LBARX has already
set to zero), the RLWINM is redundant and can be eliminated.
these redundant clear instructions are introduced by 85a9f2e148.
24 lines
793 B
LLVM
24 lines
793 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE
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define void @test(ptr %ptr, i8 %cmp, i8 %val) {
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; PPC64LE-LABEL: test:
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; PPC64LE: # %bb.0:
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; PPC64LE-NEXT: clrlwi 5, 5, 24
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; PPC64LE-NEXT: clrlwi 4, 4, 24
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; PPC64LE-NEXT: .p2align 5
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; PPC64LE-NEXT: .LBB0_1: # %cmpxchg.start
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; PPC64LE-NEXT: #
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; PPC64LE-NEXT: lbarx 6, 0, 3
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; PPC64LE-NEXT: cmplw 6, 4
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; PPC64LE-NEXT: bnelr 0
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; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore
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; PPC64LE-NEXT: #
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; PPC64LE-NEXT: stbcx. 5, 0, 3
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; PPC64LE-NEXT: bne 0, .LBB0_1
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; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end
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; PPC64LE-NEXT: blr
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%res = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic
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ret void
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}
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