a1710eb3cd
The LIT test cases were migrated with the script provided by Nikita Popov. No manual changes were made. Committed without review since no functional changes, after consultation with uweigand.
128 lines
3.7 KiB
LLVM
128 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Allocate 8 bytes, no need to align stack.
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define void @f0() {
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; CHECK-LABEL: f0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aghi %r15, -168
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; CHECK-NEXT: .cfi_def_cfa_offset 328
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; CHECK-NEXT: mvghi 160(%r15), 10
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; CHECK-NEXT: aghi %r15, 168
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; CHECK-NEXT: br %r14
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%x = alloca i64
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store volatile i64 10, ptr %x
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ret void
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}
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; Allocate ptr 8, no need to align stack.
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define void @f1(i64 %len) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
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; CHECK-NEXT: .cfi_offset %r11, -72
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: lgr %r11, %r15
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; CHECK-NEXT: .cfi_def_cfa_register %r11
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; CHECK-NEXT: lgr %r1, %r15
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; CHECK-NEXT: sllg %r0, %r2, 3
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; CHECK-NEXT: sgr %r1, %r0
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; CHECK-NEXT: la %r2, 160(%r1)
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; CHECK-NEXT: lgr %r15, %r1
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; CHECK-NEXT: mvghi 0(%r2), 10
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; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
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; CHECK-NEXT: br %r14
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%x = alloca i64, i64 %len
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store volatile i64 10, ptr %x
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ret void
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}
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; Static alloca, align 128.
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define void @f2() {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
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; CHECK-NEXT: .cfi_offset %r11, -72
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: lgr %r11, %r15
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; CHECK-NEXT: .cfi_def_cfa_register %r11
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; CHECK-NEXT: lgr %r1, %r15
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; CHECK-NEXT: aghi %r1, -128
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; CHECK-NEXT: la %r2, 280(%r1)
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; CHECK-NEXT: nill %r2, 65408
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; CHECK-NEXT: lgr %r15, %r1
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; CHECK-NEXT: mvghi 0(%r2), 10
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; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
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; CHECK-NEXT: br %r14
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%x = alloca i64, i64 1, align 128
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store volatile i64 10, ptr %x, align 128
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ret void
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}
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; Dynamic alloca, align 128.
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define void @f3(i64 %len) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
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; CHECK-NEXT: .cfi_offset %r11, -72
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: lgr %r11, %r15
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; CHECK-NEXT: .cfi_def_cfa_register %r11
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; CHECK-NEXT: lgr %r1, %r15
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; CHECK-NEXT: sllg %r0, %r2, 3
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; CHECK-NEXT: sgr %r1, %r0
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; CHECK-NEXT: lay %r15, -120(%r1)
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; CHECK-NEXT: la %r1, 160(%r1)
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; CHECK-NEXT: nill %r1, 65408
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; CHECK-NEXT: mvghi 0(%r1), 10
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; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
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; CHECK-NEXT: br %r14
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%x = alloca i64, i64 %len, align 128
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store volatile i64 10, ptr %x, align 128
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ret void
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}
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; Static alloca w/out alignment - part of frame.
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define void @f4() {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: aghi %r15, -168
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; CHECK-NEXT: .cfi_def_cfa_offset 328
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; CHECK-NEXT: mvhi 164(%r15), 10
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; CHECK-NEXT: aghi %r15, 168
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; CHECK-NEXT: br %r14
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%x = alloca i32
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store volatile i32 10, ptr %x
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ret void
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}
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; Static alloca of one i32, aligned by 128.
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define void @f5() {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
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; CHECK-NEXT: .cfi_offset %r11, -72
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: lgr %r11, %r15
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; CHECK-NEXT: .cfi_def_cfa_register %r11
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; CHECK-NEXT: lgr %r1, %r15
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; CHECK-NEXT: aghi %r1, -128
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; CHECK-NEXT: la %r2, 280(%r1)
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; CHECK-NEXT: nill %r2, 65408
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; CHECK-NEXT: lgr %r15, %r1
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; CHECK-NEXT: mvhi 0(%r2), 10
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; CHECK-NEXT: lmg %r11, %r15, 248(%r11)
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; CHECK-NEXT: br %r14
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%x = alloca i32, i64 1, align 128
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store volatile i32 10, ptr %x
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ret void
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}
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