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clang-p2996/llvm/lib/Target/AMDGPU
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serge-sans-paille 27fd01d3f8 [iwyu] Handle regressions in libLLVM header include 
Running iwyu-diff on LLVM codebase since fb67d683db detected a few
regressions, fixing them.

The impact on preprocessed output is negligible: -4k lines.
2022-06-22 18:50:39 +02:00
..
AsmParser
[llvm] Call *set::insert without checking membership first (NFC)
2022-06-18 10:22:05 -07:00
Disassembler
[AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes
2022-06-20 14:23:07 +03:00
MCA
[llvm] Use = default (NFC)
2022-02-06 22:18:35 -08:00
MCTargetDesc
[iwyu] Handle regressions in libLLVM header include
2022-06-22 18:50:39 +02:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
[AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes
2022-06-20 14:23:07 +03:00
AMDGPU.h
[AMDGPU] Adjust wave priority based on VMEM instructions to avoid duty-cycling.
2022-04-27 14:37:18 +01:00
AMDGPU.td
Reland [AMDGPU] gfx11 vop3dpp instructions
2022-06-07 14:49:13 -04:00
AMDGPUAliasAnalysis.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
AMDGPUAliasAnalysis.h
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
AMDGPUAlwaysInlinePass.cpp
[HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols
2021-10-18 16:53:15 -06:00
AMDGPUAnnotateKernelFeatures.cpp
[AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor.
2021-09-20 14:48:50 -07:00
AMDGPUAnnotateUniformValues.cpp
[AMDGPU] Return better Changed status from AMDGPUAnnotateUniformValues
2022-02-17 09:31:42 +00:00
AMDGPUArgumentUsageInfo.cpp
AMDGPU: Remove fixed function ABI option
2021-12-10 19:41:19 -05:00
AMDGPUArgumentUsageInfo.h
…
AMDGPUAsmPrinter.cpp
[AMDGPU] Update SPI_SHADER_PGM_RSRC2_PS.EXTRA_LDS_SIZE for GFX11
2022-06-21 14:48:12 +01:00
AMDGPUAsmPrinter.h
[AMDGPU] Lazily init pal metadata on first function
2022-02-04 18:39:35 +01:00
AMDGPUAtomicOptimizer.cpp
[AMDGPU] Add GFX11 llvm.amdgcn.permlane64 intrinsic
2022-06-13 21:12:11 +01:00
AMDGPUAttributes.def
AMDGPU: Emit metadata for the hidden_multigrid_sync_arg conditionally
2022-04-12 12:36:30 -07:00
AMDGPUAttributor.cpp
[Attributor][NFCI] Introduce AttributorConfig to bundle all options
2022-04-15 18:17:19 -05:00
AMDGPUCallingConv.td
[AMDGPU][NFC] Refactor AMDGPUCallingConv.td
2022-06-01 16:24:09 +00:00
AMDGPUCallLowering.cpp
[NFC] Simplify code
2022-06-20 15:15:52 +00:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Add clamp combine
2021-12-03 12:49:39 +01:00
AMDGPUCombinerHelper.cpp
[AMDGPU][GlobalISel] Fix insert point in FoldableFneg combine
2022-02-11 12:09:40 +01:00
AMDGPUCombinerHelper.h
[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
2021-11-17 14:25:13 +01:00
AMDGPUCtorDtorLowering.cpp
[amdgpu] Don't crash on empty global ctor/dtor
2021-11-16 14:36:08 +00:00
AMDGPUExportClustering.cpp
[llvm] Use = default (NFC)
2022-02-06 22:18:35 -08:00
AMDGPUExportClustering.h
…
AMDGPUFeatures.td
AMDGPU: Remove FeatureLocalMemorySize0
2021-09-02 22:43:01 -04:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
2022-06-17 09:16:59 -04:00
AMDGPUGlobalISelUtils.cpp
…
AMDGPUGlobalISelUtils.h
…
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Emit metadata for the hidden_multigrid_sync_arg conditionally
2022-04-12 12:36:30 -07:00
AMDGPUHSAMetadataStreamer.h
[llvm] Use = default (NFC)
2022-02-06 22:18:35 -08:00
AMDGPUIGroupLP.cpp
Don't use Optional::hasValue (NFC)
2022-06-20 20:05:16 -07:00
AMDGPUIGroupLP.h
[AMDGPU] Add more expressive sched_barrier controls
2022-06-14 22:03:05 -07:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row
2022-06-16 18:23:14 +01:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
[AMDGPU] Fix LOD bias in A16 combine
2022-01-21 12:09:06 +01:00
AMDGPUInstrInfo.td
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
AMDGPUInstructions.td
Reland [AMDGPU] gfx11 vop3dpp instructions
2022-06-07 14:49:13 -04:00
AMDGPUInstructionSelector.cpp
[AMDGPU] gfx11 Remove SDWA from shuffle_vector ISel
2022-06-21 14:55:00 -04:00
AMDGPUInstructionSelector.h
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
2022-06-17 09:16:59 -04:00
AMDGPUISelDAGToDAG.cpp
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
2022-06-17 09:16:59 -04:00
AMDGPUISelDAGToDAG.h
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
2022-06-17 09:16:59 -04:00
AMDGPUISelLowering.cpp
[NFC][Alignment] Remove max functions between Align and MaybeAlign
2022-06-20 08:37:48 +00:00
AMDGPUISelLowering.h
AMDGPU: Use the implicit kernargs for code object version 5
2022-03-17 14:12:36 -07:00
AMDGPULateCodeGenPrepare.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AMDGPULegalizerInfo.cpp
[AMDGPU][GlobalISel] Legalize G_FSUB for s16
2022-06-20 12:25:49 +02:00
AMDGPULegalizerInfo.h
AMDGPU/GISel: Introduce custom legalization of G_MUL
2022-06-09 13:38:56 +02:00
AMDGPULibCalls.cpp
[AMDGPU] Pull out repeated getVecSize() calls. NFC.
2022-02-10 16:31:36 +00:00
AMDGPULibFunc.cpp
Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"
2022-01-26 16:55:53 +01:00
AMDGPULibFunc.h
[llvm] Use = default (NFC)
2022-02-06 22:18:35 -08:00
AMDGPULowerIntrinsics.cpp
[iwyu] Handle regressions in libLLVM header include
2022-05-04 08:32:38 +02:00
AMDGPULowerKernelArguments.cpp
[NFC] Simplify code
2022-06-20 15:15:52 +00:00
AMDGPULowerKernelAttributes.cpp
AMDGPU: Update reqd-work-group-size optimization for umin intrinsic
2022-04-12 20:03:02 -04:00
AMDGPULowerModuleLDSPass.cpp
[amdgpu] Elide module lds allocation in kernels with no callees
2022-05-04 22:42:07 +01:00
AMDGPUMachineCFGStructurizer.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
AMDGPUMachineFunction.cpp
[amdgpu] Elide module lds allocation in kernels with no callees
2022-05-04 22:42:07 +01:00
AMDGPUMachineFunction.h
[Alignment] Use Align for MaxKernArgAlign
2022-06-22 13:40:37 +00:00
AMDGPUMachineModuleInfo.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
[AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic
2022-05-11 13:22:51 -07:00
AMDGPUMCInstLower.h
AMDGPU: Fix missing c++ mode comment
2022-06-01 21:14:48 -04:00
AMDGPUMIRFormatter.cpp
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
AMDGPUMIRFormatter.h
[llvm] Use = default (NFC)
2022-02-06 22:18:35 -08:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
[NFC] Remove unnecessary "#include"s from header files
2022-02-23 01:20:48 -08:00
AMDGPUPerfHintAnalysis.cpp
[AMDGPU][NFC] Remove isConstantAddr
2022-06-17 08:49:29 +08:00
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
AMDGPUPreLegalizerCombiner.cpp
AMDGPU: Remove redundant call to MachineInstrBuilder::setMBB
2022-05-03 07:49:20 -05:00
AMDGPUPrintfRuntimeBinding.cpp
[NFC] format InstructionSimplify & lowerCaseFunctionNames
2022-06-09 16:10:08 +02:00
AMDGPUPromoteAlloca.cpp
Use llvm::less_second (NFC)
2022-06-04 22:48:32 -07:00
AMDGPUPromoteKernelArguments.cpp
[AMDGPU] Set noclobber metadata on loads instead of cast to constant
2022-03-07 23:13:02 -08:00
AMDGPUPropagateAttributes.cpp
AMDGPU: Use attributor to propagate amdgpu-flat-work-group-size
2021-10-22 16:23:50 -04:00
AMDGPUPTNote.h
[NFC] Fix endif comments to match with include guard
2022-01-07 15:52:59 +08:00
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Fix introducing f16 fmed3 for gfx8
2022-01-19 10:43:21 -05:00
AMDGPURegisterBankInfo.cpp
[AMDGPU] Reorder cases. NFC.
2022-06-20 14:30:17 +01:00
AMDGPURegisterBankInfo.h
AMDGPU: Add G_AMDGPU_MAD_64_32 instructions
2022-05-27 12:36:17 -05:00
AMDGPURegisterBanks.td
…
AMDGPUReplaceLDSUseWithPointer.cpp
[llvm] Don't use Optional::getValue (NFC)
2022-06-20 22:45:45 -07:00
AMDGPUResourceUsageAnalysis.cpp
[AMDGPU] Define SGPR_NULL64 register. NFCI.
2022-06-13 13:23:33 -07:00
AMDGPUResourceUsageAnalysis.h
AMDGPU: Convert AMDGPUResourceUsageAnalysis to a Module pass
2022-02-04 15:56:04 -05:00
AMDGPURewriteOutArguments.cpp
[AMDGPURewriteOutArguments] Don't use pointer element type
2022-02-08 16:10:41 +01:00
AMDGPUSearchableTables.td
[AMDGPU] gfx11 ldsdir intrinsics and ISel
2022-06-17 09:03:16 -04:00
AMDGPUSetWavePriority.cpp
[AMDGPU] Adjust wave priority based on VMEM instructions to avoid duty-cycling.
2022-04-27 14:37:18 +01:00
AMDGPUSubtarget.cpp
[NFC][Alignment] Remove max functions between Align and MaybeAlign
2022-06-20 08:37:48 +00:00
AMDGPUSubtarget.h
[AMDGPU] gfx11 subtarget features & early tests
2022-05-11 10:31:49 -04:00
AMDGPUTargetMachine.cpp
[llvm] Don't use Optional::getValue (NFC)
2022-06-20 22:45:45 -07:00
AMDGPUTargetMachine.h
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
Recommit "[SLP][TTI] Refactoring of getShuffleCost Args to work like getArithmeticInstrCost"
2022-04-26 14:02:40 -07:00
AMDGPUTargetTransformInfo.h
Recommit "[SLP][TTI] Refactoring of getShuffleCost Args to work like getArithmeticInstrCost"
2022-04-26 14:02:40 -07:00
AMDGPUUnifyDivergentExitNodes.cpp
[Analysis, Target, Transforms] Construct SmallVector with iterator ranges (NFC)
2021-09-07 09:19:33 -07:00
AMDGPUUnifyMetadata.cpp
…
AMDKernelCodeT.h
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
BUFInstructions.td
[AMDGPU] Remove a duplicate atomic fadd pattern
2022-06-20 14:08:57 +01:00
CaymanInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
CMakeLists.txt
[AMDGPU] Add more expressive sched_barrier controls
2022-06-14 22:03:05 -07:00
DSInstructions.td
[AMDGPU] Add GFX11 llvm.amdgcn.ds.add.gs.reg.rtn / llvm.amdgcn.ds.sub.gs.reg.rtn intrinsics
2022-06-16 18:23:14 +01:00
EvergreenInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
EXPInstructions.td
[AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row
2022-06-16 18:23:14 +01:00
FLATInstructions.td
[AMDGPU] gfx11 FLAT Instructions
2022-05-25 15:29:39 -04:00
GCNDPPCombine.cpp
[AMDGPU] Combine DPP mov even if old reg def is in different BB
2022-05-05 11:30:31 +01:00
GCNHazardRecognizer.cpp
[AMDGPU] Add support for GFX11 LDSDIR hazards
2022-06-20 21:58:12 +01:00
GCNHazardRecognizer.h
[AMDGPU] Add support for GFX11 LDSDIR hazards
2022-06-20 21:58:12 +01:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNNSAReassign.cpp
[AMDGPU] GFX11 CodeGen support for MIMG instructions
2022-06-16 18:23:14 +01:00
GCNPreRAOptimizations.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNProcessors.td
[AMDGPU] gfx11 subtarget features & early tests
2022-05-11 10:31:49 -04:00
GCNRegPressure.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
GCNRegPressure.h
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
GCNSchedStrategy.cpp
[AMDGPU] Enable PreRARematerialize scheduling pass with multiple high RP regions
2022-04-08 13:08:32 -07:00
GCNSchedStrategy.h
[AMDGPU] Enable PreRARematerialize scheduling pass with multiple high RP regions
2022-04-08 13:08:32 -07:00
GCNSubtarget.h
[AMDGPU] Work around GFX11 flat scratch SVS swizzling bug
2022-06-13 21:00:42 +01:00
InstCombineTables.td
…
LDSDIRInstructions.td
[AMDGPU] gfx11 ldsdir intrinsics and ISel
2022-06-17 09:03:16 -04:00
MIMGInstructions.td
[AMDGPU][MC][GFX1013] Enable image_msaa_load
2022-06-10 13:42:05 +03:00
R600.h
[AMDGPU] Rename AMDGPUCFGStructurizer to R600MachineCFGStructurizer
2022-02-18 15:08:25 +00:00
R600.td
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600AsmPrinter.cpp
[MC] De-capitalize SwitchSection. NFC
2022-06-10 22:50:55 -07:00
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600ControlFlowFinalizer.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600ExpandSpecialInstrs.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600FrameLowering.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
R600InstrInfo.h
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
R600InstrInfo.td
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R600Instructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
R600ISelDAGToDAG.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600ISelLowering.cpp
[Alignment][NFC] Remove usage of MemSDNode::getAlignment
2022-06-07 13:52:20 +00:00
R600ISelLowering.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
R600MachineCFGStructurizer.cpp
[AMDGPU] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds
2022-04-19 22:36:58 -07:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
R600MachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
R600MCInstLower.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600OpenCLImageTypeLoweringPass.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
R600OptimizeVectorRegisters.cpp
[Target] Use range-based for loops (NFC)
2021-12-17 10:11:08 -08:00
R600Packetizer.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
R600Processors.td
AMDGPU: Remove FeatureLocalMemorySize0
2021-09-02 22:43:01 -04:00
R600RegisterInfo.cpp
Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"
2022-01-26 16:55:53 +01:00
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
[AMDGPU] Use default member initializers in Subtarget classes
2022-04-12 16:42:30 +01:00
R600Subtarget.h
[AMDGPU] Use default member initializers in Subtarget classes
2022-04-12 16:42:30 +01:00
R600TargetMachine.cpp
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
R600TargetMachine.h
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
R600TargetTransformInfo.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600TargetTransformInfo.h
[NFC][AMDGPU] Reduce includes dependencies.
2021-08-25 12:01:55 +03:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[AMDGPU] Return better Changed status from SIAnnotateControlFlow
2022-02-17 09:38:57 +00:00
SIDefines.h
Update *_TMPRING_SIZE.WAVESIZE for GFX11
2022-06-10 13:24:00 -04:00
SIFixSGPRCopies.cpp
[Target] Use range-based for loops (NFC)
2021-11-26 21:21:17 -08:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU] Aggressively fold immediates in SIFoldOperands
2022-05-18 10:19:35 +01:00
SIFormMemoryClauses.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
SIFrameLowering.cpp
AMDGPU: Move SpilledReg from MFI to SIRegisterInfo
2022-06-02 17:11:24 -04:00
SIFrameLowering.h
[AMDGPU] On gfx908, reserve VGPR for AGPR copy based on register budget.
2022-04-21 07:57:26 +05:30
SIInsertHardClauses.cpp
[AMDGPU] Update SIInsertHardClauses for GFX11
2022-06-09 21:29:56 +01:00
SIInsertWaitcnts.cpp
[AMDGPU] gfx11 waitcnt support for VINTERP and LDSDIR instructions
2022-06-17 09:30:37 -04:00
SIInstrFormats.td
Reland [AMDGPU] gfx11 vop3dpp instructions
2022-06-07 14:49:13 -04:00
SIInstrInfo.cpp
[AMDGPU] Add isMFMA helper function. NFC
2022-06-14 22:01:49 -07:00
SIInstrInfo.h
[AMDGPU] Mark GFX11 dual source blend export as strict-wqm
2022-06-20 21:58:12 +01:00
SIInstrInfo.td
[AMDGPU] gfx11 VOP3P instruction MC support
2022-06-08 13:32:01 -04:00
SIInstructions.td
AMDGPU: Add G_AMDGPU_MAD_64_32 instructions
2022-05-27 12:36:17 -05:00
SIISelLowering.cpp
[AMDGPU] GFX11 CodeGen support for MIMG instructions
2022-06-16 18:23:14 +01:00
SIISelLowering.h
[AMDGPU] Basic implementation of isExtractSubvectorCheap
2022-06-10 14:43:07 +01:00
SILateBranchLowering.cpp
[AMDGPU] Set GFX11 null export target based on export attributes
2022-06-21 09:40:31 +01:00
SILoadStoreOptimizer.cpp
[AMDGPU] Merge flat with global in the SILoadStoreOptimizer
2022-03-09 10:04:37 -08:00
SILowerControlFlow.cpp
AMDGPU: Fix LiveVariables error after lowering SI_END_CF
2022-04-05 21:57:50 -04:00
SILowerI1Copies.cpp
[AMDGPU] Return better Changed status from SILowerI1Copies
2022-02-17 09:38:57 +00:00
SILowerSGPRSpills.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
SIMachineFunctionInfo.cpp
[Alignment] Use Align for MaxKernArgAlign
2022-06-22 13:40:37 +00:00
SIMachineFunctionInfo.h
[Alignment] Use Align for MaxKernArgAlign
2022-06-22 13:40:37 +00:00
SIMachineScheduler.cpp
[AMDGPU]: Fix failing assertion in SIMachineScheduler
2022-04-21 14:52:29 +01:00
SIMachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIMemoryLegalizer.cpp
[llvm] Don't use Optional::getValue (NFC)
2022-06-20 22:45:45 -07:00
SIModeRegister.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
SIOptimizeExecMasking.cpp
[AMDGPU] Increase detection range for s_mov, v_cmpx transformation.
2022-04-08 12:47:24 +02:00
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
SIOptimizeVGPRLiveRange.cpp
AMDGPU: Skip unexpected CFG in SIOptimizeVGPRLiveRange
2022-06-22 12:49:41 +08:00
SIPeepholeSDWA.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
SIPostRABundler.cpp
[AMDGPU] Fix SIPostRABundler crash on null register used by dbg value
2021-11-18 17:01:19 -08:00
SIPreAllocateWWMRegs.cpp
AMDGPU: Defer creation of WWM VGPR spill slots
2022-04-19 21:07:13 -04:00
SIPreEmitPeephole.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
SIProgramInfo.cpp
…
SIProgramInfo.h
…
SIRegisterInfo.cpp
[AMDGPU] Define SGPR_NULL64 register. NFCI.
2022-06-13 13:23:33 -07:00
SIRegisterInfo.h
AMDGPU: Move SpilledReg from MFI to SIRegisterInfo
2022-06-02 17:11:24 -04:00
SIRegisterInfo.td
[AMDGPU] Define SGPR_NULL64 register. NFCI.
2022-06-13 13:23:33 -07:00
SISchedule.td
[AMDGPU] gfx11 subtarget features & early tests
2022-05-11 10:31:49 -04:00
SIShrinkInstructions.cpp
[AMDGPU] GFX11 CodeGen support for MIMG instructions
2022-06-16 18:23:14 +01:00
SIWholeQuadMode.cpp
[AMDGPU] Mark GFX11 dual source blend export as strict-wqm
2022-06-20 21:58:12 +01:00
SMInstructions.td
[AMDGPU][GFX9][GFX10] Support base+soffset+offset SMEM atomics.
2022-06-10 13:22:41 +01:00
SOPInstructions.td
[AMDGPU] New GFX11 intrinsic llvm.amdgcn.s.sendmsg.rtn
2022-06-10 08:15:23 +01:00
VIInstrFormats.td
[AMDGPU] gfx11 export instructions
2022-05-25 14:44:09 -04:00
VINTERPInstructions.td
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
2022-06-17 09:16:59 -04:00
VOP1Instructions.td
[AMDGPU] Add GFX11 codegen for llvm.amdgcn.mov.dpp8
2022-06-16 19:44:28 +01:00
VOP2Instructions.td
[AMDGPU] gfx11 support add_f16
2022-06-14 08:59:45 -04:00
VOP3Instructions.td
[AMDGPU] gfx11 new dot instruction codegen support
2022-06-16 14:19:34 -04:00
VOP3PInstructions.td
[AMDGPU] gfx11 new dot instruction codegen support
2022-06-16 14:19:34 -04:00
VOPCInstructions.td
[AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes
2022-06-20 14:23:07 +03:00
VOPInstructions.td
[AMDGPU][MC][GFX11] Correct disassembly of DPP variants of VOPC64 opcodes
2022-06-20 14:23:07 +03:00