f42f2b7005
This mostly handles folding of constants that have already become loads, but we expose some generic load cases as well. This also exposes the chance to merge unary shuffles across X86ISD::ANDNP nodes with different scalar widths
164 lines
6.6 KiB
LLVM
164 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; xor undef, undef --> 0 because it's not worth fighting to make that return undef?
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define <4 x i64> @xor_insert_insert(<2 x i64> %x, <2 x i64> %y) {
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; SSE-LABEL: xor_insert_insert:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm1, %xmm0
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: xor_insert_insert:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%xw = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%yw = shufflevector <2 x i64> %y, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%r = xor <4 x i64> %xw, %yw
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ret <4 x i64> %r
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}
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define <4 x i64> @xor_insert_insert_high_half(<2 x i64> %x, <2 x i64> %y) {
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; SSE-LABEL: xor_insert_insert_high_half:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm1
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: xor_insert_insert_high_half:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX-NEXT: retq
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%xw = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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%yw = shufflevector <2 x i64> %y, <2 x i64> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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%r = xor <4 x i64> %xw, %yw
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ret <4 x i64> %r
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}
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; All elements of the add are undefined:
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; x[0] , x[1] , x[2] , x[3], u , u , u , u
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; + u , u , u , u , 42 , 43 , 44 , 45
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define <8 x i32> @add_undef_elts(<4 x i32> %x) {
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; SSE-LABEL: add_undef_elts:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: add_undef_elts:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%bogus_bo = add <8 x i32> %extend, <i32 undef, i32 undef, i32 undef, i32 undef, i32 42, i32 43, i32 44, i32 12>
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%arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 6, i32 0, i32 5, i32 4, i32 3, i32 2, i32 1, i32 7>
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ret <8 x i32> %arbitrary_shuf
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}
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; Verify that constant operand 0 for a sub works too.
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define <8 x i32> @sub_undef_elts(<4 x i32> %x) {
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; SSE-LABEL: sub_undef_elts:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sub_undef_elts:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%bogus_bo = sub <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 42, i32 43, i32 44, i32 12>, %extend
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%arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 5, i32 4, i32 3, i32 2, i32 6, i32 7>
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ret <8 x i32> %arbitrary_shuf
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}
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; and undef, C --> 0, so this tests that we are tracking known zero lanes.
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define <4 x i64> @and_undef_elts(<2 x i64> %x) {
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; SSE-LABEL: and_undef_elts:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: and_undef_elts:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%extend = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%bogus_bo = and <4 x i64> %extend, <i64 undef, i64 undef, i64 42, i64 43>
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%arbitrary_shuf = shufflevector <4 x i64> %bogus_bo, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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ret <4 x i64> %arbitrary_shuf
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}
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; or undef, C --> -1, so this tests that we are tracking known all-ones lanes.
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define <4 x i64> @or_undef_elts(<2 x i64> %x) {
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; SSE-LABEL: or_undef_elts:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: or_undef_elts:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; AVX-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,1,2]
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; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: retq
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%extend = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%bogus_bo = or <4 x i64> %extend, <i64 undef, i64 undef, i64 42, i64 43>
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%arbitrary_shuf = shufflevector <4 x i64> %bogus_bo, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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ret <4 x i64> %arbitrary_shuf
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}
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; Verify that this isn't limited to high/low halves.
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define <8 x i32> @xor_undef_elts(<4 x i32> %x) {
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; SSE-LABEL: xor_undef_elts:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: xor_undef_elts:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 1, i32 3, i32 0, i32 2, i32 undef, i32 undef>
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%bogus_bo = xor <8 x i32> %extend, <i32 42, i32 43, i32 undef, i32 undef, i32 undef, i32 undef, i32 44, i32 12>
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%arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 6, i32 1, i32 5, i32 4, i32 3, i32 2, i32 0, i32 7>
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ret <8 x i32> %arbitrary_shuf
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}
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; Verify that this isn't limited to high/low halves
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; Special case: the undef-ness of the 1st shuffle may be lost if we turn that into vector concat.
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define <8 x i32> @xor_undef_elts_alt(<4 x i32> %x) {
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; SSE-LABEL: xor_undef_elts_alt:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: movaps {{.*#+}} xmm2 = <u,u,44,12>
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; SSE-NEXT: xorps %xmm0, %xmm2
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; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[2,0]
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[1,0]
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; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm1[0,0]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm2[2,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: xor_undef_elts_alt:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: vmovaps {{.*#+}} ymm1 = [6,1,5,4,3,2,0,7]
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; AVX-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX-NEXT: retq
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%extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef>
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%bogus_bo = xor <8 x i32> %extend, <i32 42, i32 43, i32 undef, i32 undef, i32 undef, i32 undef, i32 44, i32 12>
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%arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 6, i32 1, i32 5, i32 4, i32 3, i32 2, i32 0, i32 7>
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ret <8 x i32> %arbitrary_shuf
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}
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