bcad050106
This implements arm, armeb, thumb, thumbeb PLT entries parsing support in ELF for llvm-objdump. Implementation is similar to AArch64MCInstrAnalysis::findPltEntries. PLT entry signatures are based on LLD code for PLT generation (ARM::writePlt). llvm-objdump tests are produced from lld/test/ELF/arm-plt-reloc.s, lld/test/ELF/armv8-thumb-plt-reloc.s.
47 lines
1.3 KiB
ArmAsm
47 lines
1.3 KiB
ArmAsm
# REQUIRES: arm
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# RUN: rm -rf %t && split-file %s %t
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# RUN: llvm-mc -filetype=obj -arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %t/a.s -o %t1.o
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# RUN: llvm-mc -filetype=obj -arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %t/b.s -o %t2.o
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# RUN: ld.lld -shared %t1.o %t2.o -o %t.so
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# RUN: llvm-objdump -d %t.so | FileCheck %s
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## Check that, when the input is a mixture of objects which can and cannot use
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## the ARM ISA, we use the default ARM PLT sequences.
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# CHECK: <.plt>:
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# CHECK-NEXT: e52de004 str lr, [sp, #-0x4]!
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# CHECK-NEXT: e28fe600 add lr, pc, #0, #12
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# CHECK-NEXT: e28eea20 add lr, lr, #32, #20
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# CHECK-NEXT: e5bef084 ldr pc, [lr, #0x84]!
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# CHECK-NEXT: d4 d4 d4 d4 .word 0xd4d4d4d4
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# CHECK-NEXT: d4 d4 d4 d4 .word 0xd4d4d4d4
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# CHECK-NEXT: d4 d4 d4 d4 .word 0xd4d4d4d4
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# CHECK-NEXT: d4 d4 d4 d4 .word 0xd4d4d4d4
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# CHECK-EMPTY:
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# CHECK-NEXT: <bar@plt>:
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# CHECK-NEXT: e28fc600 add r12, pc, #0, #12
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# CHECK-NEXT: e28cca20 add r12, r12, #32, #20
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# CHECK-NEXT: e5bcf06c ldr pc, [r12, #0x6c]!
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# CHECK-NEXT: d4 d4 d4 d4 .word 0xd4d4d4d4
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#--- a.s
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.globl foo
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.type foo, %function
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.globl bar
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.type bar, %function
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.thumb
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foo:
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bl bar
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bx lr
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#--- b.s
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.eabi_attribute Tag_ARM_ISA_use, 0
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.arm
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.globl bar
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.type bar, %function
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bar:
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bx lr
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