Mohammad Bashir bcdce987c0 Fix regression tests with bad FileCheck checks (#140373) ...

Fixes https://github.com/llvm/llvm-project/issues/140149

2025-05-22 07:59:57 +03:00

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AArch64

Fix regression tests with bad FileCheck checks (#140373)

2025-05-22 07:59:57 +03:00

AMDGPU

[AMDGPU] Fix computation of waves/EU maximum (#140921)

2025-05-22 02:45:59 +02:00

ARC

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ARM

Fix regression tests with bad FileCheck checks (#140373)

2025-05-22 07:59:57 +03:00

AVR

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BPF

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CSKY

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DirectX

[DirectX] scalarize the dx.isinf intrinsic (#140638)

2025-05-20 10:26:58 -07:00

Generic

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Hexagon

Hexagon: sfmax/sfmin instructions are IEEE754-2019 (#139056)

2025-05-14 11:55:11 +08:00

Inputs

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Lanai

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LoongArch

[LoongArch] Add patterns for vstelm instructions (#139201)

2025-05-21 14:21:12 +08:00

M68k

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Mips

[COFF][Mips] Set PrivateGlobalPrefix to .L (#140033)

2025-05-16 11:22:44 +08:00

MIR

[NVPTX] Remove Float register classes (#140487)

2025-05-21 11:33:57 -07:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Remove Float register classes (#140487)

2025-05-21 11:33:57 -07:00

PowerPC

[PowerPC] catch v2i64 shift left by 1 is add case (#138772)

2025-05-13 11:26:46 -04:00

RISCV

[IA] Add support for [de]interleave{3,5,7} (#139373)

2025-05-22 04:32:47 +01:00

SPARC

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SPIRV

[SPIRV] Addition of matrix multiply accumulate operands (#138665)

2025-05-21 14:05:56 +02:00

SystemZ

[MCP] Disable BackwardCopyPropagateBlock for copies with implicit registers. (#137687)

2025-05-08 16:27:08 -07:00

Thumb

[MC][AArch64][ARM][X86] Push target-dependent assembler flags into targets (#139844)

2025-05-18 20:09:43 +01:00

Thumb2

Fix regression tests with bad FileCheck checks (#140373)

2025-05-22 07:59:57 +03:00

VE

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WebAssembly

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WinCFGuard

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WinEH

[WinEH] Fix asm in catchpad being turned into unreachable (#138392)

2025-05-08 21:46:51 +02:00

X86

[X86] lowerV8F32Shuffle - use lowerShufflePairAsUNPCKAndPermute on AVX1 targets (#140881)

2025-05-21 13:00:48 +01:00

XCore

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Xtensa

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