c09edce1b3
Previously we had a shared ID in SelectionDAGISel. AMDGPU has an initializePass function for its subclass of SelectionDAGISel. No other target does. This causes all target specific SelectionDAGISel passes to be known as "amdgpu-isel". I'm not sure what would happen if another target tried to implement an initializePass function too since the ID is already claimed. This patch gives all targets their own ID and passes it down to SelectionDAGISel constructor to MachineFunctionPass's constructor. Unfortunately, I think this causes most targets to lose print-before/after-all support for their SelectionDAGISel pass. And they probably no longer support start/stop-before/after. We can add initializePass functions to fix this as a follow up. NOTE: This was probably also broken if the AMDGPU target isn't compiled in. Step 1 to fixing PR59538. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D140161
339 lines
11 KiB
C++
339 lines
11 KiB
C++
//===-- VEISelDAGToDAG.cpp - A dag to dag inst selector for VE ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the VE target.
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//
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//===----------------------------------------------------------------------===//
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#include "VE.h"
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#include "VETargetMachine.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===--------------------------------------------------------------------===//
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/// VEDAGToDAGISel - VE specific code to select VE machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class VEDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the VE Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const VESubtarget *Subtarget;
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public:
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static char ID;
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explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(ID, tm) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<VESubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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bool selectADDRrri(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRrii(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRzri(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRzii(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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bool selectADDRzi(SDValue N, SDValue &Base, SDValue &Offset);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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StringRef getPassName() const override {
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return "VE DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "VEGenDAGISel.inc"
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private:
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SDNode *getGlobalBaseReg();
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bool matchADDRrr(SDValue N, SDValue &Base, SDValue &Index);
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bool matchADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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};
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} // end anonymous namespace
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char VEDAGToDAGISel::ID = 0;
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bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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if (Addr.getOpcode() == ISD::FrameIndex)
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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SDValue LHS, RHS;
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if (matchADDRri(Addr, LHS, RHS)) {
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if (matchADDRrr(LHS, Base, Index)) {
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Offset = RHS;
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return true;
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}
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// Return false to try selectADDRrii.
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return false;
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}
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if (matchADDRrr(Addr, LHS, RHS)) {
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// If the input is a pair of a frame-index and a register, move a
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// frame-index to LHS. This generates MI with following operands.
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// %dest, #FI, %reg, offset
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// In the eliminateFrameIndex, above MI is converted to the following.
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// %dest, %fp, %reg, fi_offset + offset
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if (isa<FrameIndexSDNode>(RHS))
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std::swap(LHS, RHS);
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if (matchADDRri(RHS, Index, Offset)) {
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Base = LHS;
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return true;
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}
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if (matchADDRri(LHS, Base, Offset)) {
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Index = RHS;
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return true;
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}
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Base = LHS;
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Index = RHS;
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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return false; // Let the reg+imm(=0) pattern catch this!
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}
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bool VEDAGToDAGISel::selectADDRrii(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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if (matchADDRri(Addr, Base, Offset)) {
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Index = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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Base = Addr;
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Index = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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bool VEDAGToDAGISel::selectADDRzri(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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// Prefer ADDRrii.
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return false;
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}
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bool VEDAGToDAGISel::selectADDRzii(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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if (isa<FrameIndexSDNode>(Addr))
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (auto *CN = dyn_cast<ConstantSDNode>(Addr)) {
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if (isInt<32>(CN->getSExtValue())) {
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Base = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Index = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Offset =
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CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool VEDAGToDAGISel::selectADDRri(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (matchADDRri(Addr, Base, Offset))
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return true;
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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bool VEDAGToDAGISel::selectADDRzi(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (isa<FrameIndexSDNode>(Addr))
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (auto *CN = dyn_cast<ConstantSDNode>(Addr)) {
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if (isInt<32>(CN->getSExtValue())) {
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Base = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Offset =
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CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool VEDAGToDAGISel::matchADDRrr(SDValue Addr, SDValue &Base, SDValue &Index) {
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if (isa<FrameIndexSDNode>(Addr))
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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; // Nothing to do here.
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} else if (Addr.getOpcode() == ISD::OR) {
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// We want to look through a transform in InstCombine and DAGCombiner that
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// turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
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if (!CurDAG->haveNoCommonBitsSet(Addr.getOperand(0), Addr.getOperand(1)))
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return false;
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} else {
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return false;
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}
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if (Addr.getOperand(0).getOpcode() == VEISD::Lo ||
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Addr.getOperand(1).getOpcode() == VEISD::Lo)
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return false; // Let the LEASL patterns catch this!
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Base = Addr.getOperand(0);
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Index = Addr.getOperand(1);
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return true;
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}
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bool VEDAGToDAGISel::matchADDRri(SDValue Addr, SDValue &Base, SDValue &Offset) {
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auto AddrTy = Addr->getValueType(0);
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), AddrTy);
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<32>(CN->getSExtValue())) {
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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// Constant offset from frame ref.
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), AddrTy);
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} else {
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Base = Addr.getOperand(0);
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}
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Offset =
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CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), MVT::i32);
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return true;
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}
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}
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return false;
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}
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void VEDAGToDAGISel::Select(SDNode *N) {
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SDLoc dl(N);
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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return; // Already selected.
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}
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switch (N->getOpcode()) {
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// Late eliminate the LEGALAVL wrapper
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case VEISD::LEGALAVL:
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ReplaceNode(N, N->getOperand(0).getNode());
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return;
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// Lower (broadcast 1) and (broadcast 0) to VM[P]0
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case VEISD::VEC_BROADCAST: {
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MVT SplatResTy = N->getSimpleValueType(0);
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if (SplatResTy.getVectorElementType() != MVT::i1)
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break;
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// Constant non-zero broadcast.
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auto BConst = dyn_cast<ConstantSDNode>(N->getOperand(0));
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if (!BConst)
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break;
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bool BCTrueMask = (BConst->getSExtValue() != 0);
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if (!BCTrueMask)
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break;
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// Packed or non-packed.
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SDValue New;
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if (SplatResTy.getVectorNumElements() == StandardVectorWidth) {
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New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(N), VE::VM0,
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MVT::v256i1);
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} else if (SplatResTy.getVectorNumElements() == PackedVectorWidth) {
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New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(N), VE::VMP0,
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MVT::v512i1);
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} else
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break;
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// Replace.
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ReplaceNode(N, New.getNode());
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return;
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}
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case VEISD::GLOBAL_BASE_REG:
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ReplaceNode(N, getGlobalBaseReg());
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return;
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}
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SelectCode(N);
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool
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VEDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintID) {
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default:
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llvm_unreachable("Unexpected asm memory constraint");
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case InlineAsm::Constraint_o:
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case InlineAsm::Constraint_m: // memory
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// Try to match ADDRri since reg+imm style is safe for all VE instructions
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// with a memory operand.
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if (selectADDRri(Op, Op0, Op1)) {
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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// Otherwise, require the address to be in a register and immediate 0.
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OutOps.push_back(Op);
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OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
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return false;
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}
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return true;
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}
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SDNode *VEDAGToDAGISel::getGlobalBaseReg() {
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Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG
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->getRegister(GlobalBaseReg, TLI->getPointerTy(CurDAG->getDataLayout()))
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.getNode();
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}
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/// createVEISelDag - This pass converts a legalized DAG into a
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/// VE-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) {
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return new VEDAGToDAGISel(TM);
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}
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