40ba0942e2
Currently, the custom SGPR spill lowering pass spills SGPRs into physical VGPR lanes and the remaining VGPRs are used by regalloc for vector regclass allocation. This imposes many restrictions that we ended up with unsuccessful SGPR spilling when there won't be enough VGPRs and we are forced to spill the leftover into memory during PEI. The custom spill handling during PEI has many edge cases and often breaks the compiler time to time. This patch implements spilling SGPRs into virtual VGPR lanes. Since we now split the register allocation for SGPRs and VGPRs, the virtual registers introduced for the spill lanes would get allocated automatically in the subsequent regalloc invocation for VGPRs. Spill to virtual registers will always be successful, even in the high-pressure situations, and hence it avoids most of the edge cases during PEI. We are now left with only the custom SGPR spills during PEI for special registers like the frame pointer which isn an unproblematic case. This patch also implements the whole wave spills which might occur if RA spills any live range of virtual registers involved in the whole wave operations. Earlier, we had been hand-picking registers for such machine operands. But now with SGPR spills into virtual VGPR lanes, we are exposing them to the allocator. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D124196
61 lines
2.5 KiB
LLVM
61 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s
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declare hidden ptr addrspace(1) @ext(ptr addrspace(1))
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define ptr addrspace(1) @call_assert_align() {
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; CHECK-LABEL: call_assert_align:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s16, s33
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; CHECK-NEXT: s_mov_b32 s33, s32
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; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1
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; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b64 exec, s[18:19]
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; CHECK-NEXT: ; implicit-def: $vgpr40
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; CHECK-NEXT: s_addk_i32 s32, 0x400
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; CHECK-NEXT: v_writelane_b32 v40, s30, 0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: v_writelane_b32 v41, s16, 0
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; CHECK-NEXT: v_writelane_b32 v40, s31, 1
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, ext@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, ext@rel32@hi+12
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: global_store_dword v[0:1], v2, off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readlane_b32 s31, v40, 1
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; CHECK-NEXT: v_readlane_b32 s30, v40, 0
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; CHECK-NEXT: v_readlane_b32 s4, v41, 0
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; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
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; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
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; CHECK-NEXT: s_mov_b64 exec, s[6:7]
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; CHECK-NEXT: s_addk_i32 s32, 0xfc00
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; CHECK-NEXT: s_mov_b32 s33, s4
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%call = call align 4 ptr addrspace(1) @ext(ptr addrspace(1) null)
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store volatile i32 0, ptr addrspace(1) %call
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ret ptr addrspace(1) %call
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}
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define ptr addrspace(1) @tail_call_assert_align() {
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; CHECK-LABEL: tail_call_assert_align:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, ext@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, ext@rel32@hi+12
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; CHECK-NEXT: s_setpc_b64 s[16:17]
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entry:
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%call = tail call align 4 ptr addrspace(1) @ext(ptr addrspace(1) null)
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ret ptr addrspace(1) %call
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}
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