40ba0942e2
Currently, the custom SGPR spill lowering pass spills SGPRs into physical VGPR lanes and the remaining VGPRs are used by regalloc for vector regclass allocation. This imposes many restrictions that we ended up with unsuccessful SGPR spilling when there won't be enough VGPRs and we are forced to spill the leftover into memory during PEI. The custom spill handling during PEI has many edge cases and often breaks the compiler time to time. This patch implements spilling SGPRs into virtual VGPR lanes. Since we now split the register allocation for SGPRs and VGPRs, the virtual registers introduced for the spill lanes would get allocated automatically in the subsequent regalloc invocation for VGPRs. Spill to virtual registers will always be successful, even in the high-pressure situations, and hence it avoids most of the edge cases during PEI. We are now left with only the custom SGPR spills during PEI for special registers like the frame pointer which isn an unproblematic case. This patch also implements the whole wave spills which might occur if RA spills any live range of virtual registers involved in the whole wave operations. Earlier, we had been hand-picking registers for such machine operands. But now with SGPR spills into virtual VGPR lanes, we are exposing them to the allocator. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D124196
71 lines
3.1 KiB
LLVM
71 lines
3.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SGPR %s
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; Make sure this doesn't crash.
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; ALL-LABEL: {{^}}test:
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; ALL: s_mov_b32 s[[LO:[0-9]+]], SCRATCH_RSRC_DWORD0
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; ALL: s_mov_b32 s[[HI:[0-9]+]], 0xe80000
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; Make sure we are handling hazards correctly.
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; SGPR: v_mov_b32_e32 v0, vcc_lo
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; SGPR-NEXT: s_or_saveexec_b64 [[EXEC_COPY:s\[[0-9]+:[0-9]+\]]], -1
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; SGPR-NEXT: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:4 ; 4-byte Folded Reload
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; SGPR-NEXT: s_mov_b64 exec, [[EXEC_COPY]]
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; SGPR-NEXT: s_waitcnt vmcnt(0)
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; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 0
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; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 1
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; SGPR-NEXT: v_readlane_b32 s{{[0-9]+}}, [[VHI]], 2
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; SGPR-NEXT: v_readlane_b32 s[[HI:[0-9]+]], [[VHI]], 3
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; SGPR-NEXT: s_nop 4
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; SGPR-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; ALL: s_endpgm
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define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 %in) {
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call void asm sideeffect "", "~{s[0:7]}" ()
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call void asm sideeffect "", "~{s[8:15]}" ()
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call void asm sideeffect "", "~{s[16:23]}" ()
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call void asm sideeffect "", "~{s[24:31]}" ()
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call void asm sideeffect "", "~{s[32:39]}" ()
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call void asm sideeffect "", "~{s[40:47]}" ()
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call void asm sideeffect "", "~{s[48:55]}" ()
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call void asm sideeffect "", "~{s[56:63]}" ()
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call void asm sideeffect "", "~{s[64:71]}" ()
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call void asm sideeffect "", "~{s[72:79]}" ()
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call void asm sideeffect "", "~{s[80:87]}" ()
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call void asm sideeffect "", "~{s[88:95]}" ()
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call void asm sideeffect "", "~{v[0:7]}" ()
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call void asm sideeffect "", "~{v[8:15]}" ()
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call void asm sideeffect "", "~{v[16:23]}" ()
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call void asm sideeffect "", "~{v[24:31]}" ()
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call void asm sideeffect "", "~{v[32:39]}" ()
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call void asm sideeffect "", "~{v[40:47]}" ()
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call void asm sideeffect "", "~{v[48:55]}" ()
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call void asm sideeffect "", "~{v[56:63]}" ()
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call void asm sideeffect "", "~{v[64:71]}" ()
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call void asm sideeffect "", "~{v[72:79]}" ()
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call void asm sideeffect "", "~{v[80:87]}" ()
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call void asm sideeffect "", "~{v[88:95]}" ()
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call void asm sideeffect "", "~{v[96:103]}" ()
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call void asm sideeffect "", "~{v[104:111]}" ()
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call void asm sideeffect "", "~{v[112:119]}" ()
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call void asm sideeffect "", "~{v[120:127]}" ()
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call void asm sideeffect "", "~{v[128:135]}" ()
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call void asm sideeffect "", "~{v[136:143]}" ()
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call void asm sideeffect "", "~{v[144:151]}" ()
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call void asm sideeffect "", "~{v[152:159]}" ()
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call void asm sideeffect "", "~{v[160:167]}" ()
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call void asm sideeffect "", "~{v[168:175]}" ()
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call void asm sideeffect "", "~{v[176:183]}" ()
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call void asm sideeffect "", "~{v[184:191]}" ()
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call void asm sideeffect "", "~{v[192:199]}" ()
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call void asm sideeffect "", "~{v[200:207]}" ()
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call void asm sideeffect "", "~{v[208:215]}" ()
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call void asm sideeffect "", "~{v[216:223]}" ()
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call void asm sideeffect "", "~{v[224:231]}" ()
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call void asm sideeffect "", "~{v[232:239]}" ()
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call void asm sideeffect "", "~{v[240:247]}" ()
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call void asm sideeffect "", "~{v[248:255]}" ()
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store i32 %in, i32 addrspace(1)* %out
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ret void
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}
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