40ba0942e2
Currently, the custom SGPR spill lowering pass spills SGPRs into physical VGPR lanes and the remaining VGPRs are used by regalloc for vector regclass allocation. This imposes many restrictions that we ended up with unsuccessful SGPR spilling when there won't be enough VGPRs and we are forced to spill the leftover into memory during PEI. The custom spill handling during PEI has many edge cases and often breaks the compiler time to time. This patch implements spilling SGPRs into virtual VGPR lanes. Since we now split the register allocation for SGPRs and VGPRs, the virtual registers introduced for the spill lanes would get allocated automatically in the subsequent regalloc invocation for VGPRs. Spill to virtual registers will always be successful, even in the high-pressure situations, and hence it avoids most of the edge cases during PEI. We are now left with only the custom SGPR spills during PEI for special registers like the frame pointer which isn an unproblematic case. This patch also implements the whole wave spills which might occur if RA spills any live range of virtual registers involved in the whole wave operations. Earlier, we had been hand-picking registers for such machine operands. But now with SGPR spills into virtual VGPR lanes, we are exposing them to the allocator. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D124196
258 lines
9.3 KiB
LLVM
258 lines
9.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=si-pre-allocate-wwm-regs -o %t.mir %s
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; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
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; Test that SIMachineFunctionInfo can be round trip serialized through
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; MIR.
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@lds = addrspace(3) global [512 x float] undef, align 4
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; CHECK-LABEL: {{^}}name: kernel
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; CHECK: machineFunctionInfo:
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; CHECK-NEXT: explicitKernArgSize: 128
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; CHECK-NEXT: maxKernArgAlign: 64
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; CHECK-NEXT: ldsSize: 2048
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; CHECK-NEXT: gdsSize: 0
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; CHECK-NEXT: dynLDSAlign: 1
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; CHECK-NEXT: isEntryFunction: true
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; CHECK-NEXT: noSignedZerosFPMath: false
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; CHECK-NEXT: memoryBound: false
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; CHECK-NEXT: waveLimiter: false
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; CHECK-NEXT: hasSpilledSGPRs: false
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; CHECK-NEXT: hasSpilledVGPRs: false
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; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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; CHECK-NEXT: frameOffsetReg: '$fp_reg'
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; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
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; CHECK-NEXT: bytesInStackArgArea: 0
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; CHECK-NEXT: returnsVoid: true
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; CHECK-NEXT: argumentInfo:
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; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
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; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
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; CHECK-NEXT: mode:
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; CHECK-NEXT: ieee: true
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; CHECK-NEXT: dx10-clamp: true
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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; CHECK-NEXT: highBitsOf32BitAddress: 0
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; CHECK-NEXT: occupancy: 10
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; CHECK-NEXT: vgprForAGPRCopy: ''
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; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
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; CHECK-NEXT: body:
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define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
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%gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
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store float 0.0, float addrspace(3)* %gep, align 4
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ret void
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}
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@gds = addrspace(2) global [128 x i32] undef, align 4
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; CHECK-LABEL: {{^}}name: ps_shader
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; CHECK: machineFunctionInfo:
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; CHECK-NEXT: explicitKernArgSize: 0
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; CHECK-NEXT: maxKernArgAlign: 4
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; CHECK-NEXT: ldsSize: 0
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; CHECK-NEXT: gdsSize: 512
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; CHECK-NEXT: dynLDSAlign: 1
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; CHECK-NEXT: isEntryFunction: true
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; CHECK-NEXT: noSignedZerosFPMath: false
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; CHECK-NEXT: memoryBound: false
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; CHECK-NEXT: waveLimiter: false
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; CHECK-NEXT: hasSpilledSGPRs: false
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; CHECK-NEXT: hasSpilledVGPRs: false
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; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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; CHECK-NEXT: frameOffsetReg: '$fp_reg'
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; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
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; CHECK-NEXT: bytesInStackArgArea: 0
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; CHECK-NEXT: returnsVoid: true
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; CHECK-NEXT: argumentInfo:
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; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
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; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
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; CHECK-NEXT: mode:
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; CHECK-NEXT: ieee: false
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; CHECK-NEXT: dx10-clamp: true
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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; CHECK-NEXT: highBitsOf32BitAddress: 0
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; CHECK-NEXT: occupancy: 10
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; CHECK-NEXT: vgprForAGPRCopy: ''
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; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
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; CHECK-NEXT: body:
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define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
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%gep = getelementptr inbounds [128 x i32], [128 x i32] addrspace(2)* @gds, i32 0, i32 %arg0
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atomicrmw add i32 addrspace(2)* %gep, i32 8 seq_cst
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ret void
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}
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; CHECK-LABEL: {{^}}name: gds_size_shader
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; CHECK: gdsSize: 4096
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define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 {
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ret void
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}
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; CHECK-LABEL: {{^}}name: function
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; CHECK: machineFunctionInfo:
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; CHECK-NEXT: explicitKernArgSize: 0
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; CHECK-NEXT: maxKernArgAlign: 1
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; CHECK-NEXT: ldsSize: 0
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; CHECK-NEXT: gdsSize: 0
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; CHECK-NEXT: dynLDSAlign: 1
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; CHECK-NEXT: isEntryFunction: false
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; CHECK-NEXT: noSignedZerosFPMath: false
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; CHECK-NEXT: memoryBound: false
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; CHECK-NEXT: waveLimiter: false
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; CHECK-NEXT: hasSpilledSGPRs: false
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; CHECK-NEXT: hasSpilledVGPRs: false
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; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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; CHECK-NEXT: frameOffsetReg: '$sgpr33'
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; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
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; CHECK-NEXT: bytesInStackArgArea: 0
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; CHECK-NEXT: returnsVoid: true
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; CHECK-NEXT: argumentInfo:
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; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }
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; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' }
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; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' }
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; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' }
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; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' }
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; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' }
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; CHECK-NEXT: LDSKernelId: { reg: '$sgpr15' }
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; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' }
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; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 }
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; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 }
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; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 }
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; CHECK-NEXT: mode:
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; CHECK-NEXT: ieee: true
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; CHECK-NEXT: dx10-clamp: true
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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; CHECK-NEXT: highBitsOf32BitAddress: 0
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; CHECK-NEXT: occupancy: 10
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; CHECK-NEXT: vgprForAGPRCopy: ''
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; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
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; CHECK-NEXT: body:
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define void @function() {
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ret void
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}
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; CHECK-LABEL: {{^}}name: function_nsz
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; CHECK: machineFunctionInfo:
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; CHECK-NEXT: explicitKernArgSize: 0
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; CHECK-NEXT: maxKernArgAlign: 1
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; CHECK-NEXT: ldsSize: 0
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; CHECK-NEXT: gdsSize: 0
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; CHECK-NEXT: dynLDSAlign: 1
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; CHECK-NEXT: isEntryFunction: false
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; CHECK-NEXT: noSignedZerosFPMath: true
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; CHECK-NEXT: memoryBound: false
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; CHECK-NEXT: waveLimiter: false
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; CHECK-NEXT: hasSpilledSGPRs: false
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; CHECK-NEXT: hasSpilledVGPRs: false
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; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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; CHECK-NEXT: frameOffsetReg: '$sgpr33'
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; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
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; CHECK-NEXT: bytesInStackArgArea: 0
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; CHECK-NEXT: returnsVoid: true
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; CHECK-NEXT: argumentInfo:
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; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' }
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; CHECK-NEXT: queuePtr: { reg: '$sgpr6_sgpr7' }
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; CHECK-NEXT: dispatchID: { reg: '$sgpr10_sgpr11' }
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; CHECK-NEXT: workGroupIDX: { reg: '$sgpr12' }
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; CHECK-NEXT: workGroupIDY: { reg: '$sgpr13' }
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; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr14' }
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; CHECK-NEXT: LDSKernelId: { reg: '$sgpr15' }
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; CHECK-NEXT: implicitArgPtr: { reg: '$sgpr8_sgpr9' }
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; CHECK-NEXT: workItemIDX: { reg: '$vgpr31', mask: 1023 }
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; CHECK-NEXT: workItemIDY: { reg: '$vgpr31', mask: 1047552 }
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; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 }
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; CHECK-NEXT: mode:
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; CHECK-NEXT: ieee: true
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; CHECK-NEXT: dx10-clamp: true
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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; CHECK-NEXT: highBitsOf32BitAddress: 0
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; CHECK-NEXT: occupancy: 10
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; CHECK-NEXT: vgprForAGPRCopy: ''
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; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
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; CHECK-NEXT: body:
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define void @function_nsz() #0 {
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ret void
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}
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; CHECK-LABEL: {{^}}name: function_dx10_clamp_off
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; CHECK: mode:
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; CHECK-NEXT: ieee: true
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; CHECK-NEXT: dx10-clamp: false
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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define void @function_dx10_clamp_off() #1 {
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ret void
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}
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; CHECK-LABEL: {{^}}name: function_ieee_off
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; CHECK: mode:
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; CHECK-NEXT: ieee: false
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; CHECK-NEXT: dx10-clamp: true
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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define void @function_ieee_off() #2 {
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ret void
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}
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; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off
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; CHECK: mode:
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; CHECK-NEXT: ieee: false
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; CHECK-NEXT: dx10-clamp: false
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; CHECK-NEXT: fp32-input-denormals: true
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; CHECK-NEXT: fp32-output-denormals: true
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; CHECK-NEXT: fp64-fp16-input-denormals: true
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; CHECK-NEXT: fp64-fp16-output-denormals: true
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define void @function_ieee_off_dx10_clamp_off() #3 {
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ret void
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}
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; CHECK-LABEL: {{^}}name: high_address_bits
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; CHECK: machineFunctionInfo:
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; CHECK: highBitsOf32BitAddress: 4294934528
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define amdgpu_ps void @high_address_bits() #4 {
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ret void
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}
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; CHECK-LABEL: {{^}}name: wwm_reserved_regs
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; CHECK: wwmReservedRegs:
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; CHECK-NEXT: - '$vgpr2'
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; CHECK-NEXT: - '$vgpr3'
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define amdgpu_cs void @wwm_reserved_regs(i32 addrspace(1)* %ptr, <4 x i32> inreg %tmp14) {
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%ld0 = load volatile i32, i32 addrspace(1)* %ptr
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%ld1 = load volatile i32, i32 addrspace(1)* %ptr
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%inactive0 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld1, i32 0)
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%inactive1 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %ld0, i32 0)
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store volatile i32 %inactive0, i32 addrspace(1)* %ptr
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store volatile i32 %inactive1, i32 addrspace(1)* %ptr
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ret void
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}
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declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #6
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attributes #0 = { "no-signed-zeros-fp-math" = "true" }
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attributes #1 = { "amdgpu-dx10-clamp" = "false" }
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attributes #2 = { "amdgpu-ieee" = "false" }
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attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
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attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
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attributes #5 = { "amdgpu-gds-size"="4096" }
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attributes #6 = { convergent nounwind readnone willreturn }
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