af64948e2a
Summary: Adds the constraints described below to ensure that we can tie variables of SVE ACLE types to operands in inline-asm: - y: SVE registers Z0-Z7 - Upl: One of the low eight SVE predicate registers (P0-P7) - Upa: Full range of SVE predicate registers (P0-P15) Reviewers: sdesmalen, huntergr, rovka, cameron.mcinally, efriedma, rengolin Reviewed By: efriedma Subscribers: miyuki, tschuett, rkruppe, psnobl, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D75690
22 lines
513 B
C
22 lines
513 B
C
// REQUIRES: aarch64-registered-target
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// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns \
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// RUN: -target-feature +neon -S -O1 -o - %s | FileCheck %s
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// Assembler error
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// Output constraint : Set a vector constraint on an integer
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__SVFloat32_t funcB2()
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{
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__SVFloat32_t ret ;
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asm volatile (
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"fmov %[ret], wzr \n"
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: [ret] "=w" (ret)
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:
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:);
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return ret ;
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}
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// CHECK: funcB2
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// CHECK-ERROR: error: invalid operand for instruction
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