0928368f62
This adds the Arm Optimized Routines (see https://github.com/ARM-software/optimized-routines) source code under the the LLVM license. The version of the code provided in this patch is v20.02 of the Arm Optimized Routines project. This entire contribution is being committed as is even though it does not currently fit the LLVM libc model and does not follow the LLVM coding style. In the near future, implementations from this patch will be moved over to their right place in the LLVM-libc tree. This will be done over many small patches, all of which will go through the normal LLVM code review process. See this libc-dev post for the plan: http://lists.llvm.org/pipermail/libc-dev/2020-March/000044.html Differential revision of the original upload: https://reviews.llvm.org/D75355
116 lines
2.2 KiB
ArmAsm
116 lines
2.2 KiB
ArmAsm
/*
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* memset - fill memory with a constant byte
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
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*
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*/
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#include "../asmdefs.h"
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#define dstin x0
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#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define zva_val x5
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ENTRY (__memset_aarch64)
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dup v0.16B, valw
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add dstend, dstin, count
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cmp count, 96
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b.hi L(set_long)
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cmp count, 16
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b.hs L(set_medium)
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mov val, v0.D[0]
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/* Set 0..15 bytes. */
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tbz count, 3, 1f
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str val, [dstin]
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str val, [dstend, -8]
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ret
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nop
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1: tbz count, 2, 2f
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str valw, [dstin]
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str valw, [dstend, -4]
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ret
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2: cbz count, 3f
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strb valw, [dstin]
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tbz count, 1, 3f
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strh valw, [dstend, -2]
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3: ret
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/* Set 17..96 bytes. */
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L(set_medium):
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str q0, [dstin]
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tbnz count, 6, L(set96)
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str q0, [dstend, -16]
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tbz count, 5, 1f
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str q0, [dstin, 16]
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str q0, [dstend, -32]
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1: ret
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.p2align 4
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/* Set 64..96 bytes. Write 64 bytes from the start and
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32 bytes from the end. */
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L(set96):
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str q0, [dstin, 16]
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stp q0, q0, [dstin, 32]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 4
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L(set_long):
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and valw, valw, 255
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bic dst, dstin, 15
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str q0, [dstin]
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cmp count, 160
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ccmp valw, 0, 0, hs
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b.ne L(no_zva)
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#ifndef SKIP_ZVA_CHECK
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mrs zva_val, dczid_el0
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and zva_val, zva_val, 31
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cmp zva_val, 4 /* ZVA size is 64 bytes. */
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b.ne L(no_zva)
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#endif
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str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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bic dst, dst, 63
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sub count, dstend, dst /* Count is now 64 too large. */
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sub count, count, 128 /* Adjust count and bias for loop. */
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.p2align 4
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L(zva_loop):
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add dst, dst, 64
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dc zva, dst
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subs count, count, 64
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b.hi L(zva_loop)
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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L(no_zva):
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sub count, dstend, dst /* Count is 16 too large. */
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sub dst, dst, 16 /* Dst is biased by -32. */
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sub count, count, 64 + 16 /* Adjust count and bias for loop. */
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L(no_zva_loop):
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stp q0, q0, [dst, 32]
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stp q0, q0, [dst, 64]!
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subs count, count, 64
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b.hi L(no_zva_loop)
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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END (__memset_aarch64)
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