657e067bb5
This follows other patches that changed printing immediate values of branch instructions to target addresses, see D76580 (x86), D76591 (PPC), D77853 (AArch64). As observing immediate values might sometimes be useful, they are printed as comments for branch instructions. // llvm-objdump -d output (before) 000200b4 <_start>: 200b4: ff ff ff fa blx #-4 <thumb> 000200b8 <thumb>: 200b8: ff f7 fc ef blx #-8 <_start> // llvm-objdump -d output (after) 000200b4 <_start>: 200b4: ff ff ff fa blx 0x200b8 <thumb> @ imm = #-4 000200b8 <thumb>: 200b8: ff f7 fc ef blx 0x200b4 <_start> @ imm = #-8 // GNU objdump -d. 000200b4 <_start>: 200b4: faffffff blx 200b8 <thumb> 000200b8 <thumb>: 200b8: f7ff effc blx 200b4 <_start> Differential Revision: https://reviews.llvm.org/D104701
119 lines
3.6 KiB
ArmAsm
119 lines
3.6 KiB
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
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// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-arm-thumb-abs.s -o %tfar
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// RUN: echo "SECTIONS { \
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// RUN: . = 0xb4; \
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// RUN: .callee1 : { *(.callee_low) } \
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// RUN: .callee2 : { *(.callee_arm_low) } \
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// RUN: .caller : { *(.text) } \
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// RUN: .callee3 : { *(.callee_high) } \
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// RUN: .callee4 : { *(.callee_arm_high) } } " > %t.script
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// RUN: ld.lld --script %t.script %t %tfar -o %t2
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// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t2 | FileCheck %s
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/// Test BLX instruction is chosen for ARM BL/BLX instruction and Thumb callee
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/// Using two callees to ensure at least one has 2-byte alignment.
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.syntax unified
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.thumb
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.section .callee_low, "ax",%progbits
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.align 2
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.type callee_low,%function
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callee_low:
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bx lr
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.type callee_low2, %function
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callee_low2:
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bx lr
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.section .callee_arm_low, "ax",%progbits
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.arm
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.balign 0x100
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.type callee_arm_low,%function
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.align 2
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callee_arm_low:
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bx lr
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.section .text, "ax",%progbits
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.arm
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.globl _start
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.balign 0x10000
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.type _start,%function
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_start:
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bl callee_low
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blx callee_low
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bl callee_low2
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blx callee_low2
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bl callee_high
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blx callee_high
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bl callee_high2
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blx callee_high2
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bl blx_far
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blx blx_far2
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/// blx to ARM instruction should be written as a BL
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bl callee_arm_low
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blx callee_arm_low
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bl callee_arm_high
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blx callee_arm_high
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bx lr
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.section .callee_high, "ax",%progbits
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.balign 0x100
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.thumb
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.type callee_high,%function
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callee_high:
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bx lr
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.type callee_high2,%function
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callee_high2:
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bx lr
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.section .callee_arm_high, "ax",%progbits
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.arm
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.balign 0x100
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.type callee_arm_high,%function
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callee_arm_high:
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bx lr
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// CHECK: Disassembly of section .callee1:
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// CHECK-EMPTY:
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// CHECK-NEXT: <callee_low>:
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// CHECK-NEXT: b4: 70 47 bx lr
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// CHECK: <callee_low2>:
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// CHECK-NEXT: b6: 70 47 bx lr
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// CHECK: Disassembly of section .callee2:
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// CHECK-EMPTY:
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// CHECK-NEXT: <callee_arm_low>:
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// CHECK-NEXT: 100: 1e ff 2f e1 bx lr
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// CHECK: Disassembly of section .caller:
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// CHECK-EMPTY:
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// CHECK-NEXT: <_start>:
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// CHECK-NEXT: 10000: 2b c0 ff fa blx 0xb4 <callee_low>
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// CHECK-NEXT: 10004: 2a c0 ff fa blx 0xb4 <callee_low>
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// CHECK-NEXT: 10008: 29 c0 ff fb blx 0xb6 <callee_low2>
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// CHECK-NEXT: 1000c: 28 c0 ff fb blx 0xb6 <callee_low2>
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// CHECK-NEXT: 10010: 3a 00 00 fa blx 0x10100 <callee_high>
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// CHECK-NEXT: 10014: 39 00 00 fa blx 0x10100 <callee_high>
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// CHECK-NEXT: 10018: 38 00 00 fb blx 0x10102 <callee_high2>
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// CHECK-NEXT: 1001c: 37 00 00 fb blx 0x10102 <callee_high2>
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/// 0x2010024 = blx_far
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// CHECK-NEXT: 10020: ff ff 7f fa blx 0x2010024
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/// 0x2010028 = blx_far2
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// CHECK-NEXT: 10024: ff ff 7f fa blx 0x2010028
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// CHECK-NEXT: 10028: 34 c0 ff eb bl 0x100 <callee_arm_low>
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// CHECK-NEXT: 1002c: 33 c0 ff eb bl 0x100 <callee_arm_low>
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// CHECK-NEXT: 10030: 72 00 00 eb bl 0x10200 <callee_arm_high>
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// CHECK-NEXT: 10034: 71 00 00 eb bl 0x10200 <callee_arm_high>
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// CHECK-NEXT: 10038: 1e ff 2f e1 bx lr
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// CHECK: Disassembly of section .callee3:
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// CHECK-EMPTY:
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// CHECK: <callee_high>:
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// CHECK-NEXT: 10100: 70 47 bx lr
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// CHECK: <callee_high2>:
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// CHECK-NEXT: 10102: 70 47 bx lr
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// CHECK: Disassembly of section .callee4:
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// CHECK-EMPTY:
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// CHECK-NEXT: <callee_arm_high>:
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// CHECK-NEXT: 10200: 1e ff 2f e1 bx lr
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