657e067bb5
This follows other patches that changed printing immediate values of branch instructions to target addresses, see D76580 (x86), D76591 (PPC), D77853 (AArch64). As observing immediate values might sometimes be useful, they are printed as comments for branch instructions. // llvm-objdump -d output (before) 000200b4 <_start>: 200b4: ff ff ff fa blx #-4 <thumb> 000200b8 <thumb>: 200b8: ff f7 fc ef blx #-8 <_start> // llvm-objdump -d output (after) 000200b4 <_start>: 200b4: ff ff ff fa blx 0x200b8 <thumb> @ imm = #-4 000200b8 <thumb>: 200b8: ff f7 fc ef blx 0x200b4 <_start> @ imm = #-8 // GNU objdump -d. 000200b4 <_start>: 200b4: faffffff blx 200b8 <thumb> 000200b8 <thumb>: 200b8: f7ff effc blx 200b4 <_start> Differential Revision: https://reviews.llvm.org/D104701
212 lines
8.3 KiB
ArmAsm
212 lines
8.3 KiB
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf --arm-add-build-attributes %s -o %t.o
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// RUN: ld.lld --fix-cortex-a8 -verbose %t.o -o %t2 2>&1 | FileCheck %s
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// RUN: llvm-objdump -d %t2 --start-address=0x29004 --stop-address=0x29024 --no-show-raw-insn | FileCheck --check-prefix=CHECK-PATCHES %s
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// RUN: llvm-objdump -d %t2 --start-address=0x21ffa --stop-address=0x22002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE1 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x22ffa --stop-address=0x23002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE2 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x23ffa --stop-address=0x24002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE3 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x24ff4 --stop-address=0x25002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE4 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x25ffa --stop-address=0x26002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE5 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x26ffa --stop-address=0x27002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE6 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x27ffa --stop-address=0x28002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE7 %s
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// RUN: llvm-objdump -d %t2 --start-address=0x28ff4 --stop-address=0x29002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE8 %s
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// RUN: ld.lld --fix-cortex-a8 -verbose -r %t.o -o %t3 2>&1 | FileCheck --check-prefix=CHECK-RELOCATABLE-LLD %s
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// RUN: llvm-objdump --no-show-raw-insn -d %t3 --start-address=0xffa --stop-address=0x1002 | FileCheck --check-prefix=CHECK-RELOCATABLE %s
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// CHECK: ld.lld: detected cortex-a8-657419 erratum sequence starting at 22FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 23FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 24FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 25FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 26FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 27FFE in unpatched output.
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// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 28FFE in unpatched output.
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/// We do not detect errors when doing a relocatable link as we don't know what
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/// the final addresses are.
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// CHECK-RELOCATABLE-LLD-NOT: ld.lld: detected cortex-a8-657419 erratum sequence
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/// Basic tests for the -fix-cortex-a8 erratum fix. The full details of the
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/// erratum and the patch are in ARMA8ErrataFix.cpp . The test creates an
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/// instance of the erratum every 4KiB (32-bit non-branch, followed by 32-bit
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/// branch instruction, where the branch instruction spans two 4 KiB regions,
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/// and the branch destination is in the first 4KiB region.
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///
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/// Test each 32-bit branch b.w, bcc.w, bl, blx. For b.w, bcc.w, and bl we
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/// check the relocated and non-relocated forms. The blx instruction
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/// always has a relocation in assembler.
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.syntax unified
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.thumb
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.text
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.global _start
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.type _start, %function
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.balign 4096
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.thumb_func
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_start:
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nop.w
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.space 4086
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.thumb_func
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.global target
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.type target, %function
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target:
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/// 32-bit Branch spans 2 4KiB regions, preceded by a 32-bit non branch
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/// instruction, expect a patch.
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nop.w
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b.w target
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// CALLSITE1: 00021ffa <target>:
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// CALLSITE1-NEXT: 21ffa: nop.w
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// CALLSITE1-NEXT: 21ffe: b.w 0x29004 <__CortexA8657417_21FFE>
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/// Expect no patch when doing a relocatable link ld -r.
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// CHECK-RELOCATABLE: 00000ffa <target>:
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// CHECK-RELOCATABLE-NEXT: ffa: nop.w
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// CHECK-RELOCATABLE-NEXT: ffe: b.w {{.+}} @ imm = #-4
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.space 4088
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.type target2, %function
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.local target2
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target2:
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/// 32-bit Branch and link spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch.
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nop.w
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bl target2
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// CALLSITE2: 00022ffa <target2>:
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// CALLSITE2-NEXT: 22ffa: nop.w
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// CALLSITE2-NEXT: 22ffe: bl 0x29008 <__CortexA8657417_22FFE>
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.space 4088
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.type target3, %function
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.local target3
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target3:
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/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch.
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nop.w
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beq.w target3
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// CALLSITE3: 00023ffa <target3>:
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// CALLSITE3-NEXT: 23ffa: nop.w
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// CALLSITE3-NEXT: 23ffe: beq.w 0x2900c <__CortexA8657417_23FFE>
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.space 4082
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.type target4, %function
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.local target4
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.arm
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target4:
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bx lr
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.space 2
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.thumb
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/// 32-bit Branch link and exchange spans 2 4KiB regions, preceded by a
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/// 32-bit non branch instruction, blx always goes via relocation. Expect
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/// a patch.
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nop.w
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blx target4
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/// Target = 0x19010 __CortexA8657417_15FFE
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// CALLSITE4: 00024ff4 <target4>:
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// CALLSITE4-NEXT: 24ff4: bx lr
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// CALLSITE4: 24ff8: 00 00 .short 0x0000
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// CALLSITE4: 24ffa: nop.w
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// CALLSITE4-NEXT: 24ffe: blx 0x29010 <__CortexA8657417_24FFE>
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/// Separate sections for source and destination of branches to force
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/// a relocation.
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.section .text.0, "ax", %progbits
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.balign 2
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.global target5
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.type target5, %function
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target5:
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nop.w
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.section .text.1, "ax", %progbits
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.space 4084
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/// 32-bit branch spans 2 4KiB regions, preceded by a 32-bit non branch
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/// instruction, expect a patch. Branch to global symbol so goes via a
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/// relocation.
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nop.w
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b.w target5
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/// Target = 0x19014 __CortexA8657417_16FFE
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// CALLSITE5: 25ffa: nop.w
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// CALLSITE5-NEXT: 25ffe: b.w 0x29014 <__CortexA8657417_25FFE>
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.section .text.2, "ax", %progbits
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.balign 2
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.global target6
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.type target6, %function
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target6:
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nop.w
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.section .text.3, "ax", %progbits
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.space 4084
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/// 32-bit branch and link spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch. Branch to global symbol so
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/// goes via a relocation.
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nop.w
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bl target6
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/// Target = 0x19018 __CortexA8657417_17FFE
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// CALLSITE6: 26ffa: nop.w
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// CALLSITE6-NEXT: 26ffe: bl 0x29018 <__CortexA8657417_26FFE>
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.section .text.4, "ax", %progbits
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.global target7
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.type target7, %function
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target7:
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nop.w
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.section .text.5, "ax", %progbits
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.space 4084
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/// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
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/// non branch instruction, expect a patch. Branch to global symbol so
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/// goes via a relocation.
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nop.w
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bne.w target7
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// CALLSITE7: 27ffa: nop.w
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// CALLSITE7-NEXT: 27ffe: bne.w 0x2901c <__CortexA8657417_27FFE>
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.section .text.6, "ax", %progbits
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.space 4082
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.arm
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.global target8
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.type target8, %function
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target8:
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bx lr
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.section .text.7, "ax", %progbits
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.space 2
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.thumb
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/// 32-bit Branch link spans 2 4KiB regions, preceded by a 32-bit non branch
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/// instruction, expect a patch. The target of the BL is in ARM state so we
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/// expect it to be turned into a BLX. The patch must be in ARM state to
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/// avoid a state change thunk.
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nop.w
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bl target8
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// CALLSITE8: 00028ff4 <target8>:
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// CALLSITE8-NEXT: 28ff4: bx lr
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// CALLSITE8: 28ff8: 00 00 .short 0x0000
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// CALLSITE8: 28ffa: nop.w
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// CALLSITE8-NEXT: 28ffe: blx 0x29020 <__CortexA8657417_28FFE>
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// CHECK-PATCHES: 00029004 <__CortexA8657417_21FFE>:
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// CHECK-PATCHES-NEXT: 29004: b.w 0x21ffa <target>
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// CHECK-PATCHES: 00029008 <__CortexA8657417_22FFE>:
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// CHECK-PATCHES-NEXT: 29008: b.w 0x22ffa <target2>
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// CHECK-PATCHES: 0002900c <__CortexA8657417_23FFE>:
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// CHECK-PATCHES-NEXT: 2900c: b.w 0x23ffa <target3>
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// CHECK-PATCHES: 00029010 <__CortexA8657417_24FFE>:
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// CHECK-PATCHES-NEXT: 29010: b 0x24ff4 <target4>
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// CHECK-PATCHES: 00029014 <__CortexA8657417_25FFE>:
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// CHECK-PATCHES-NEXT: 29014: b.w 0x25002 <target5>
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// CHECK-PATCHES: 00029018 <__CortexA8657417_26FFE>:
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// CHECK-PATCHES-NEXT: 29018: b.w 0x26002 <target6>
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// CHECK-PATCHES: 0002901c <__CortexA8657417_27FFE>:
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// CHECK-PATCHES-NEXT: 2901c: b.w 0x27002 <target7>
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// CHECK-PATCHES: 00029020 <__CortexA8657417_28FFE>:
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// CHECK-PATCHES-NEXT: 29020: b 0x28ff4 <target8>
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